Storage test circuit

Abstract

Each signal generating circuit for generating a CS signal, an address signal, a data signal or an R / W signal of a memory to be tested, and a test setting control circuit for generating a control data of these signal generating circuits are provided. The signal generating circuits and the test setting control circuit have shift registers, and a control data and a test data are serially input to these shift registers from external terminals.

Description

technical field [0001] The present invention relates to a memory test circuit, and more particularly, to a test circuit for a semiconductor integrated circuit memory in which memory and logic are mixedly mounted on one semiconductor chip. Background technique [0002] In recent years, various LSIs such as ASICs and microprocessors have been proposed in which memories are mixedly incorporated in logic sections. In such an LSI, a signal from the logic section controls the normal operation of the memory, for example, when a read command is issued from the logic section, the memory outputs data of a selected address to the logic section. Similarly, the memory outputs the data of the selected address to the logic part. In such an LSI, since it is impractical to test the memory through a complicated logic section, various dedicated test circuits for testing the memory have been proposed. [0003] FIG. 10 is a view showing the structure of a conventional memory test circuit (refe...

AI Technical Summary

Problems solved by technology

On the other hand, in the BIST circuit shown in Fig. 11, the increase in area due to the incorporation of the RAM test command memory inside the LSI and the testing of the RAM test command memory itself are also problems

In the BIST circuit proposed in Patent Document 2, although the area increase due to the increase of the RAM test command memory does not occur, due to the extraction of the program from the scan path register inside the LSI used as a substitute for the RAM test memory Area increase due to signal lines, etc. and deterioration of wiring characteristics during design are problematic

Also, since these test circuits generate test patterns from programs, there are disadvantages in that, in the RAM test control circuit and test pattern generator, circuits for decoding programs, generating control signals for RAM, etc. are required, and the circuit size becomes large

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