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Memory cell, memory device and manufacturing method of memory cell

A storage unit and manufacturing method technology, applied in the direction of static memory, digital memory information, electrical components, etc., can solve the problems of shortening effective gate length and deterioration of transistor characteristics, and achieve the reduction of forward threshold voltage and the change of resistance Efficient, easy-to-achieve effects

Inactive Publication Date: 2004-11-03
SHARP KK
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, since the diffusion layers of the source and drain regions of the transistor (MOSFET) constituting the external circuit of the memory device are enlarged and the effective gate length is shortened due to an increase in the number of heat treatments, the characteristics of the transistor are deteriorated by the short channel effect

Method used

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  • Memory cell, memory device and manufacturing method of memory cell
  • Memory cell, memory device and manufacturing method of memory cell
  • Memory cell, memory device and manufacturing method of memory cell

Examples

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Embodiment 1

[0094] Figure 6 to Figure 12 is a schematic diagram illustrating the manufacturing steps of Embodiment 1 of the memory cell manufacturing method according to the present invention. In each figure, a memory cell area (hereinafter referred to as memory area) in which memory cells are formed and an external circuit area (hereinafter referred to as external area) in which external circuits are formed are shown on the left and right sides, respectively. Each figure shows a cross-sectional structure of a memory cell (a series circuit of a Schottky diode and an adjustable resistance element) and an external circuit (N-channel MOSFET used in the external circuit shown in the example) in manufacturing steps. In addition, in each figure, oblique lines indicating cross-sections are omitted. Although MOSFETs are usually composed of P-channel MOSFETs and N-channel MOSFETs, only N-channel MOSFETs are shown here for simplicity.

[0095] Figure 6 It is a schematic diagram describing when...

Embodiment 2

[0108] Figure 13 to Figure 20 is a schematic diagram illustrating the manufacturing steps of the second embodiment of the memory cell manufacturing method according to the present invention. In each figure, a memory cell area in which memory cells are formed (hereinafter referred to as memory area) and an external circuit area in which external circuits are formed (hereinafter referred to as external area) are shown on the left and right sides, respectively. Each figure shows a cross-sectional structure of a memory cell (a series circuit of a Schottky diode and an adjustable resistance element) and an external circuit (N-channel MOSFET used in the external circuit shown in the example) in manufacturing steps. In the memory area, an external circuit (part of the external circuit, etc.) may be provided at the lower portion of the memory cell, taking the external circuit as an example, a MOSFET is shown formed at the lower portion of the memory cell. In addition, in each figure...

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Abstract

A memory cell (33) in which a variable resistive element (31) and a Schottky diode (32) are connected in series to each other. In a memory device, bit lines (BL0, BL1 and BL2) are arranged in a column direction, one end of the bit line (BL) is connected to a bit line decoder (34), and the other end thereof is connected to a reading circuit (37). Word lines (WL0, WL1 and WL2) are arranged in a row direction so as to intersect with the bit lines (BL), and both ends of the word line (WL) are connected to word line decoders (35 and 36). In other words, the bit line (BL) and the word line (WL) are arranged in a matrix and a memory cell (33) is located at a position where the bit line (BL) and the word line (WL) intersect with each other, which constitutes the memory device. An influence of a reading disturbance in the memory cell (33) and the memory device is reduced.

Description

technical field [0001] The present invention relates to a storage unit of 1D1R type (the unit cell is composed of a diode and an adjustable resistance element) composed of a series circuit of an adjustable resistance element and a Schottky diode, and relates to setting these storage units in a matrix. A memory device for a cell and a method for manufacturing the memory cell. Background technique [0002] Many MRAMs (Magnetic Random Access Memory) currently being developed are formed by forming a ferromagnetic memory cell for storing information through residual magnetism of a ferromagnetic material of a giant magnetoresistive material. The change in resistance value generated by the difference between the magnetization directions is converted into a voltage. There are metal wires for writing in the ferromagnetic memory cell, and the magnetization direction of the ferromagnetic memory cell changes in the magnetic field generated when milliampere-level current flows through t...

Claims

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Application Information

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IPC IPC(8): G11C11/15G11C13/00H01L27/10H01L27/24
CPCH01L45/1675G11C13/0069H01L45/1233H01L45/147G11C2213/31G11C2213/72H01L45/04H01L27/24G11C13/0007G11C2013/009G11C11/15H10B63/20H10N70/20H10N70/8836H10N70/826H10N70/063
Inventor 森本英德
Owner SHARP KK
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