Semiconductor device for domain crossing

Abstract

An apparatus, for use in a semiconductor device, for providing a domain crossing operation. The apparatus includes a domain crossing sensing block, in response to an operation mode signal, first and second delay locked loop (DLL) clock signals and a CAS latency, generates a plurality of selection signals. An output enable signal generator, in response to the plurality of selection signals, generates a plurality of output enable signals. A data control block, in response to the output enable signals and the CAS latency, controls a data output operation in the semiconductor device. Each of a plurality of data align block, in response to the selection signals, the first and second DLL clock signals and an address signal, aligns data corresponding to the address signal in the data output operation.

Description

technical field [0001] The invention relates to a semiconductor device, in particular to a synchronous dynamic random access memory SDRAM and double data rate DDR, DDRII and DDRIII SDRAM semiconductor devices for domain cross-connection. Background technique [0002] Generally, semiconductor memory devices experience domain cross-connection during operation. For example, some blocks use an internal clock as a reference for operation while other blocks use a delay-locked loop (DLL) clock as a reference for operation. In addition, the transition from receiver localization to transmitter localization is governed by domain cross-connection effects. [0003] FIG. 1 is a block diagram of a semiconductor device for domain cross-connect included in a conventional memory device. [0004] As shown in the figure, the conventional memory device includes: a first flip-flop 131, a memory unit 140, a second flip-flop 150, a plurality of pipeline locking circuits 180, a driver 190, a thir...

AI Technical Summary

Problems solved by technology

However, if the operation of the semiconductor system becomes faster due to this, multiple flip-flops that delay the DLL clock become unstable because the settling time of each flip-flop cannot be guaranteed

Therefore, the total delay time ΔT of the output enable signal cannot be fixed in response to the CAS latency CL

Therefore, there is no guarantee that the data output enable signal ROUTEN can be activated in response to the CAS latency CL

[0029] In addition, abnormal operation of the semiconductor system may be caused by low power voltage, temperature and complex procedures, etc.

If the settling time of each flip-flop included in the high-frequency semiconductor system cannot be sufficiently guaranteed, it is easy to cause the high-frequency semiconductor system to malfunction

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