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Synchronous single nort SRAM capable of realizng synchronous double port SRAM effect and its realizing method

An implementation method and a technology of corresponding functions, which are applied in the field of synchronous single-port SRAM and its implementation, can solve problems such as increased chip costs, and achieve the effect of reducing the volume

Inactive Publication Date: 2004-12-15
VIMICRO CORP
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Problems solved by technology

It will also increase the cost of the chip a lot when used in large quantities

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  • Synchronous single nort SRAM capable of realizng synchronous double port SRAM effect and its realizing method
  • Synchronous single nort SRAM capable of realizng synchronous double port SRAM effect and its realizing method
  • Synchronous single nort SRAM capable of realizng synchronous double port SRAM effect and its realizing method

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Embodiment Construction

[0019] Refer to attached figure 1 , 2 , is a synchronous single-port SRAM write and read timing diagram.

[0020] The port signals of synchronous single-port SRAM generally include data input terminal D, data output terminal Q, address ADDR, clock CLK, block enable terminal CEN, write enable terminal WEN, and read enable terminal OEN; the port signals of synchronous dual-port SRAM are: Two such sets of signals: DA, DB, QA, QB, AA, AB, CLKA, CLKB, CENA, CENB, WENA, WENB, OENA, OENB. Sometimes write enable and read enable use a line WEN / OE, where tcyc is the clock cycle, tckl is the low time of the clock, tckh is the high time of the clock, tas is the address establishment time, and tah is the address Hold time, tds is the input data setup time, tdh is the address input data hold time, tws is the write signal setup time, twh is the write signal hold time, tcs is the block enable signal setup time, tch is the block enable signal hold time, When writing synchronous single-port ...

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Abstract

The present invention relates to the field of integrated circuit technology, and is especially synchronous single-port SRAM capable of realizing the synchronous double-port SRAM function and its realizing method. The synchronous single-port SRAM includes: one common SRAM body, and one mapping logic circuit module with several inputs and several outputs. The mapping logic circuit module has signal ports for connection to the synchronous SRAM body, signal ports suitable for connection to synchronous double-port SRAM, and mapping connection between the synchronous SRAM body and the signal ports for connection to synchronous double-port SRAM.

Description

technical field [0001] The invention relates to the field of integrated circuits, in particular to a synchronous single-port SRAM capable of realizing the function of a synchronous dual-port SRAM (static random access memory) and a method for realizing the same. Background technique [0002] With the development of the field of integrated circuits, people have higher and higher requirements for chip functions. Especially in the design of multimedia and communication integrated circuits, a large number of SRAMs are integrated, and dual-port SRAMs are often used. The difference between it and single-port SRAMs is that it has two sets of clock / data / address ports, and can be independently and simultaneously Write and read operations, but compared to single-port SRAM, its volume is almost twice that of single-port SRAM. It will also increase the cost of the chip a lot when used in large quantities. Contents of the invention [0003] The object of the present invention is to p...

Claims

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Application Information

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IPC IPC(8): G11C11/413H01L27/10
Inventor 朱哲金传恩
Owner VIMICRO CORP
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