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Cutting multiplying accumulating unit with parallel processing

A technology of multiplication and accumulation and parallel processing, which is applied in the field of digital signal processors, can solve problems such as reducing the performance of large multipliers, and achieve the effects of saving area, small performance, and improving coding efficiency

Inactive Publication Date: 2005-02-23
INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This is unthinkable in DSP applications
Moreover, this method uses a small multiplier to fight a large multiplier, which reduces the performance of the large multiplier

Method used

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  • Cutting multiplying accumulating unit with parallel processing
  • Cutting multiplying accumulating unit with parallel processing
  • Cutting multiplying accumulating unit with parallel processing

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Embodiment Construction

[0020] see figure 1 , the present invention a kind of parallel processing separable multiplication accumulation unit, which comprises: a partial product generation unit 21, a partial accumulation accumulation array 22, a divisible accumulator 23 constitutes; wherein the output end of the partial product generation unit 21 is connected The input end of the partial accumulation array 22; the output end of the partial accumulation array 22 is connected to the input end of the divisible accumulator 23; using this structure to realize 32-bit, 16-bit and 8-bit multiplication and accumulation operations.

[0021] Wherein the divisible partial product generating unit 21 is composed of 32 sub-generating units 41 (such as Figure 4 ), wherein the sub-generating unit is composed of an AND gate 51 and a two-input gate 52, wherein the output of the gate 52 is connected to an input of 51; the divisible partial product generating unit is according to different modes The control signals gene...

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Abstract

A multiplication accumulating unit comprising partial product accumulating array, partial product generating unit and divisible accumulator is featured as connecting output end of partial products generating unit to input end of accumulating array with its output end being connected with input end of accumulator. It can carry out multiplication accumulating operation for 32 position, 16 position and 8 position.

Description

technical field [0001] The invention relates to the field of digital signal processors. Specifically, it relates to a divisible digital signal processor data channel—a divisible multiply-accumulate unit for parallel processing. Background technique [0002] A large number of multiplication and accumulation operations are required in digital signal processing, so the multiplication and accumulation unit is an important part of the digital signal processor. The current digital signal processing requires the processing of multimedia data, and the processing of multimedia data requires increasing the throughput of 16-bit and 8-bit data and the flexibility of bit width. However, in general digital signal processors, the multiply-accumulate unit only performs operations with a fixed bit width, which brings great inconvenience to multimedia processing applications. For example, in MPEG-4, the operation requires the flexibility of the bit width from 8 bits to 64 bits. In addition...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F7/38
Inventor 姜小波陈杰
Owner INST OF MICROELECTRONICS CHINESE ACAD OF SCI
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