Test structure for a single-sided buried strap dram memory cell data array

Abstract

A test structure for determining the electrical properties of a memory cell in a matrix-like cell array constructed on the basis of the single-sided buried strap concept has a connection between internal electrodes in the storage capacitors in two adjacent memory cells in the direction of the row of active regions in order to produce a series circuit. A first selection transistor and a first storage capacitor in a first memory cell and a second selection transistor and a second storage capacitor in a second memory cell, the active regions of the first and second selection transistors not being connected between the first and second selection transistors via a contact-making bit line.

Description

technical field [0001] The present invention relates to a test structure for determining the electronic characteristics of memory cells, especially the electronic characteristics of select transistors in memory cells of single-sides buried strap DRAM memory cell arrays. Background technique [0002] A dynamic random access memory (DRAM) includes an array of storage cells connected in columns via word lines and in rows via bit lines. Data is read from or written to the memory cell due to appropriate wordline and bitline drive. A dynamic memory cell usually includes a select transistor and a storage capacitor. The select transistor is generally a field effect transistor (field effect transistor) of horizontal design and includes two diffusion regions separated by a channel with a gate connected to a character line. One of the diffusion regions of the selection transistor is connected to a bit line, and the other diffusion region is connected to a storage capacitor. Applying...

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