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Method for preparing pitch of semiconductor

A manufacturing method and semiconductor technology, applied in semiconductor/solid-state device manufacturing, electrical components, circuits, etc., can solve problems such as impracticality of lithography technology

Active Publication Date: 2005-06-15
MACRONIX INT CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0004] With the current trend of pursuing thin, light and small electronic devices and high-speed signal transmission, the pitch of semiconductors will be smaller than 200 nanometers, or even reach 100 nanometers, resulting in the current lithography technology will not be practical enough
However, if the function of the stepper scanner is to be upgraded, the semiconductor industry will also pay a huge expense

Method used

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  • Method for preparing pitch of semiconductor
  • Method for preparing pitch of semiconductor
  • Method for preparing pitch of semiconductor

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0015] Please refer to Figure 2A-2L , which is a cross-sectional flow diagram of a method for manufacturing a semiconductor pitch according to Embodiment 1 of the present invention. First, in Figure 2A Among them, a substrate 202 is provided, such as a silicon substrate, and a gate oxide (gate oxide) layer 204, a first polysilicon (poly silicon) layer 206, a silicon nitride (silicon nitride) layer are sequentially formed on the substrate 202 , SiN) layer 208 , a second polysilicon layer 210 and a patterned photoresist layer (photo resist) 212 . The patterned photoresist layer 212 has a pitch P1 and a number of openings 211, the size S1 of the openings 211 is half of the pitch P1, and P1 is the sum of the line width (line width) W1 and the size S1 of the openings 211 . For example, when a stepper scanner (scanner) with a wavelength of 193 nanometers (nm) is used for lithography, the pitch P1 is 200 nanometers (nm), and the line width W1 and the size S1 of the opening 211 a...

Embodiment 2

[0024] Please refer to Figures 3A-3H , is a cross-sectional view showing the flow of the semiconductor pitch manufacturing method according to the second embodiment of the present invention. First, in Figure 3A In the present invention, a substrate 302 is provided, such as a silicon substrate, and a gate oxide layer 304 , a polysilicon layer 306 , a silicon nitride layer 308 and a patterned photoresist layer 312 are sequentially formed on the substrate 302 . The patterned photoresist layer 312 has a pitch P1 and a number of openings 311 , the size S1 of the openings 311 is half of the pitch P1 , and P1 is the sum of the line width W1 and the size S1 of the openings 211 . For example, when a stepper scanner with a wavelength of 193 nm is used for lithography, the pitch P1 is 200 nm, and the line width W1 and the size S1 of the opening 211 are both 100 nm.

[0025] Next, trim the patterned photoresist layer 312 to form a trimmed photoresist layer 312a, such as Figure 3B sh...

Embodiment 3

[0029] Please refer to Figure 4A ~ 4K , is a cross-sectional view showing the flow of the semiconductor pitch manufacturing method according to the third embodiment of the present invention. First, in Figure 4A In, a substrate 402 is provided, such as a silicon substrate, and a gate oxide layer 404, a polysilicon layer 406, a first silicon nitride layer 408, a second silicon nitride layer 409 and a The photoresist layer 412 is patterned. The patterned photoresist layer 412 has a pitch P1 and a plurality of openings 411 , the size S1 of the openings 411 is half of the pitch P1 , and P1 is the sum of the line width W1 and the size S1 of the openings 411 . For example, when a stepper scanner with a wavelength of 193 nm is used for lithography, the pitch P1 is 200 nm, and the line width W1 and the size S1 of the opening 411 are both 100 nm.

[0030] Next, trim the patterned photoresist layer 412 to form a trimmed photoresist layer 412a, such as Figure 4B shown. exist Fig...

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Abstract

A gate oxide layer, polycrystalline silicon layer and patterned silicon nitride layer are formed in sequence on base plate. The patterned silicon nitride layer possesses first pitch and several first openings. Size of each first opening is a quarter of first pitch. Patterned oxide layer in first pitch and several second openings is formed to fill in first opening and covers part of patterned silicon nitride layer. Second openings and inferior first openings are alternating arranged. Size of second opening is a quarter of first pitch. Removing exposed patterned silicon nitride layer forms another patterned silicon nitride layer in second pitch, several openings and first openings. Second pitch is equal to half of first pitch, and first openings and third openings are alternatively arranged. Size of each third opening is a half of second pitch. Removing patterned oxide layer and exposed first polycrystalline silicon layer forms first polycrystalline silicon layer in second pitch.

Description

【Technical field】 [0001] The present invention relates to a method of manufacturing a semiconductor pitch, and more particularly relates to a method of manufacturing a semiconductor pitch smaller than the pitch specification of a step-and-scan machine. 【Background technique】 [0002] In today's era of rapid technological development, electronic devices have become an indispensable part of modern life. Wherein, the reason why the electronic device can operate is that an integrated circuit (integrated circuit, IC), such as a logic IC and a storage IC, is installed inside it. These ICs must be completed through semiconductor production, and in semiconductor production, lithography technology has been recognized as the most challenging and difficult part of production. With the continuous improvement of the step scanner (scanner), its exposure wavelength is continuously deduced. At present, in order to make the production technology of 0.25-0.18 microns (μm), the wavelength of ...

Claims

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Application Information

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IPC IPC(8): H01L21/00
Inventor 钟维民
Owner MACRONIX INT CO LTD