Method of programming electrons onto a floating gate of a non-volatile memory cell

Abstract

A memory cell has a trench formed into a surface of a semiconductor substrate, and spaced apart source and drain regions with a channel region formed therebetween. The source region is formed underneath the trench, and the channel region includes a first portion extending vertically along a sidewall of the trench and a second portion extending horizontally along the substrate surface. An electrically conductive floating gate is disposed in the trench adjacent to and insulated from the channel region first portion. An electrically conductive control gate is disposed over and insulated from the channel region second portion. A block of conductive material has at least a lower portion thereof disposed in the trench adjacent to and insulated from the floating gate, and can be electrically connected to the source region. A method of programming the cell comprises the steps of creating an inversion layer in the second portion of the channel. A stream of electrons is generated at the drain region which is adjacent to the inversion layer, and the stream of electrons is passed through the inversion layer, reaching a pinch off point. The electrons are accelerated through the depletion region by the field lines from the floating gate, with little or no scattering, causing the electrons to be accelerated through the insulator, separating the floating gate from the substrate, and injected onto the floating gate.

Description

[0001] This application claims priority to US Patent Application No. 10 / 757,830, filed January 13,2004. U.S. Patent Application No. 10 / 757,830 is a continuation-in-part of co-pending application 10 / 358,623, filed February 4, 2003, which claims the titled " High Coupling Non-Volatile Trench Memory Cell "U.S. Provisional Application No. 60 / 370,888, filed July 2, 2002, entitled " Non-Volatile Memory Trench Cell and Method of Making Same "of U.S. Provisional Application No. 60 / 393,696 and filed July 23, 2002 and entitled " Non-Volatile Memory Trench Cell With Buried Floating Gate Priority to U.S. Provisional Application No. 60 / 398,146, the entire contents of which are hereby incorporated by reference. technical field [0002] The invention relates to a self-alignment method for forming a semiconductor memory array of a floating gate memory unit. The invention also relates to a semiconductor memory array of floating gate memory cells of the above type. Background technique ...

AI Technical Summary

Problems solved by technology

Although the purpose of the stepped channel is to more efficiently inject hot electrons onto the floating gate, these memory designs suffer from drawbacks in that it is difficult to achieve the size and formation of the memory cell elements necessary for efficient and reliable operation. Optimizing the operating parameters of

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