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Cost reducing method for RCS interconnected circuit with multi-output and multi-input

A technology of interconnecting circuits and multiple outputs, applied in electrical digital data processing, special data processing applications, instruments, etc., can solve numerical instability, cannot guarantee system passivity after order reduction and 2k-order block moment matching at the same time, Unable to guarantee the passive characteristics of the system after order reduction

Inactive Publication Date: 2005-07-27
FUDAN UNIV
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Problems solved by technology

However, when directly applied to the first-order system representation of RCS interconnection circuits, PRIMA cannot guarantee the passive properties of the reduced-order system
In the second-order system model reduction technology, the ENOR[5] and SMOR[4] algorithms have the problems of numerical instability and limited moment matching accuracy respectively. The SAPOR proposed in the literature [8] is a numerically stable binary The first-order system model algorithm can guarantee the passive characteristics of the system after order reduction, and at the same time ensure accurate moment matching, but SAPOR is only suitable for RCS interconnection circuits with single input and single output
[0036] (2) For the special circuit system of B=L, PRIMA cannot guarantee the passivity and 2k-order block-moment matching of the reduced-order system at the same time
Therefore, the reduced-order system obtained by SMOR cannot exactly match the moments of the original system, and the moment matching accuracy cannot be guaranteed

Method used

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  • Cost reducing method for RCS interconnected circuit with multi-output and multi-input
  • Cost reducing method for RCS interconnected circuit with multi-output and multi-input
  • Cost reducing method for RCS interconnected circuit with multi-output and multi-input

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specific Embodiment approach

[0197] The present invention is further illustrated below by specific examples.

[0198] right figure 1 The 16-bit bus circuit shown (including two shielded wires) can be obtained by using the corresponding parameter extraction tool to obtain an equivalent RCS circuit. The circuit contains 16 current sources, and the output of the circuit is the output node voltage of 16 interconnecting lines. There are 1746 unknown variables in the RCS equivalent circuit, including 1170 node voltages and 576 inductor susceptance currents. We use the frequency response of the output node of the first interconnection line when only the current source of the first interconnection line is effective as a standard to measure the accuracy of the reduction order.

[0199] We use the algorithm of the present invention to perform reduced-order simulation on the 16-bit bus circuit. Taking the order reduction as 240 as an example, the specific steps are as follows.

[0200] Step 1: For the bus circui...

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Abstract

An order reducing method includes setting up second order system equation to describe the interconnected circuit, carrying out frequency shift and linearization for the secondary system, using second order block Arnoldi algorithm to obtain a set of orthogonal standard base, obtaining order reduced secondary system by orthogonal projection, linearizaing the secondary system to be primary circuit equation with block structure in original secondary equation for obtaining small size RCS equivalent circuit.

Description

technical field [0001] The invention belongs to the field of model reduction of linear circuits, and in particular relates to a method for reducing the order of a multi-input multi-output RCS interconnection circuit. technical background [0002] Integrated circuits have been developed to the point where electronic systems containing more than 1 billion devices can be integrated on a single chip, that is, System on One Chip (SOC). For millions of large-scale circuits, how to quickly and accurately simulate and verify the correctness of its design within a reasonable time has become a bottleneck in the design of system-on-chip (SOC). According to statistics, the time for SOC chip simulation verification has accounted for 70% of the entire design time. [0003] In the ultra-high-speed ultra-deep sub-micron SOC design, the performance of interconnect lines greatly affects the performance of the entire chip. Crosstalk and delay problems when signals propagate on interconnect l...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 曾璇苏仰锋童家榕刘榜
Owner FUDAN UNIV
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