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Non-volatile memory element and its making method

A non-volatile storage and manufacturing method technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problem of variation, storage efficiency impact, contact area reduction between top silicon oxide layer and polysilicon gate, etc. problems, to achieve the effect of simple manufacturing process and improved storage efficiency

Inactive Publication Date: 2005-10-05
POWERCHIP SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] However, with the development trend of component miniaturization, the line width of the component is also reduced, which leads to the reduction of the contact area between the top silicon oxide layer of the silicon / silicon oxide / silicon nitride / silicon oxide / silicon storage element and the polysilicon gate. , making its storage efficiency affected and deteriorated

Method used

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  • Non-volatile memory element and its making method
  • Non-volatile memory element and its making method
  • Non-volatile memory element and its making method

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Experimental program
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Embodiment Construction

[0030] Figure 2A to Figure 2D It is a sectional view of the manufacturing process of a non-volatile memory element according to a preferred embodiment of the present invention.

[0031] Please refer to Figure 2A Firstly, a substrate 200 is provided, and then a trench 202 is formed in the substrate 200 . The step of forming the trench 202 in the substrate 200 is, for example, to form a pad oxide layer (not shown) on the substrate 200 first, and then form a patterned mask layer (patterned mask layer, not shown) on the pad oxide layer. shown), the material thereof is, for example, silicon nitride or other suitable materials. Subsequently, using the patterned mask layer as a mask, the exposed pad oxide layer and part of the substrate 200 are removed. After that, after the trench 202 is formed, the pad oxide layer and the patterned mask layer need to be removed.

[0032] Next, please refer to Figure 2B A bottom oxide layer 204 is formed on the surface of the substrate 200 a...

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Abstract

First, the method forms a groove on substrate provided. Next, a bottom oxidation layer, a charge trap layer and a top oxidation layer are formed in sequence on substrate and surface of groove. Then, a conductive layer is formed on the top oxidation layer to fill in the groove, and another conductive layer is defined to form a grid pole on the groove. Finally, the top oxidation layer, the charge trap layer and the bottom oxidation layer located out of the grid pole are removed, and a preparation procedure of adulteration for source / drain poles is carried out. Since memory elements are made in groove, thus increasing coupling rate can raise storage efficiency; more charge number can be stored by adjusting depth of groove.

Description

technical field [0001] The present invention relates to a manufacturing method of a storage element, in particular to a non-volatile memory device (non-volatile memory device) and a manufacturing method thereof. Background technique [0002] Among all kinds of non-volatile memory products, it has the advantages of multiple data storage, reading, erasing, etc., and the stored data will not disappear after power off. Programmable read-only memory (EEPROM), has become a widely used memory component in personal computers and electronic equipment. A typical EEPROM uses doped polysilicon to make a floating gate and a control gate. When the memory is programmed, the electrons injected into the floating gate are uniformly distributed throughout the polysilicon floating gate layer. However, when there are defects in the tunneling oxide layer under the polysilicon floating gate layer, it is easy to cause leakage current of the device, which affects the reliability of the device. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/8247H10B69/00
Inventor 许汉杰张格荥
Owner POWERCHIP SEMICON CORP