Integrated plating and planarization process and apparatus therefor
Patent Information
- Authority / Receiving Office
- CN · China
- Current Assignee / Owner
- GLOBALFOUNDRIES INC
- Publication Date
- 2005-12-07
- Estimated Expiration
- Not applicable · inactive patent
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Abstract
Description
technical field
[0001] This invention relates to semiconductor processing, and more particularly to methods and apparatus for electroplating and planarizing copper layers on semiconductor wafers. Background technique
[0002] Deposition and selective removal of metal layers are important processes in semiconductor device fabrication. A typical semiconductor wafer has several layers of metal deposited or plated on its surface, each successive layer being polished or etched before additional layers are added. In general, electroplating copper on wafer surfaces is an extensively skilled process. Chemical-mechanical polishing (CMP) is usually performed after copper electroplating (usually a capping layer of copper is produced on the wafer) to remove unwanted portions of the electroplating. When fabricating damascene structures, the CMP process can also be used to electrically isolate damascene wiring.
[0003] Figure 1A is a schematic diagram of a typical apparatus for electr...