Integrated plating and planarization process and apparatus therefor

A planarization, equipment technology, used in the field of semiconductor processing

Inactive Publication Date: 2005-12-07
GLOBALFOUNDRIES INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

This equipment is used only for planarization (i.e., removal of mate...

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  • Integrated plating and planarization process and apparatus therefor
  • Integrated plating and planarization process and apparatus therefor
  • Integrated plating and planarization process and apparatus therefor

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Embodiment Construction

[0026] According to the present invention, an apparatus is provided that allows CMP to be performed after metal deposition (electroplating) and metal removal (electroetching) in optional steps, where each step has discrete process conditions and does not require Remove the wafer from the device. Copper plating and removal will be described to illustrate the invention. It should be understood that the present invention is not limited to the type of material deposited on the wafer.

[0027] Embodiments of the present invention may be understood as modifications of CMP equipment. A conventional CMP apparatus is schematically shown in Fig. ID. Wafer 1 is fixed upwards on wafer carrier 12 which rotates relative to table 10 with polishing pad 20 and polishing slurry thereon. The polishing rate is determined in part by the force with which the wafer 1 is pressed against the polishing pad 20 . Thus, the wafer carrier 12 is adjustable to provide a variable force on the polishing pa...

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Abstract

A method and apparatus are described for performing both electroplating of a metal layer and planarization of the layer on a substrate. Electroplating and electroetching of metal (such as copper) are performed in a repeated sequence, followed by chemical-mechanical polishing. An electroplating solution, electroetching solution, and a non-abrasive slurry are dispensed on a polishing pad in the respective process steps. The substrate is held against the pad with a variable force in accordance with the process, so that the spacing between substrate and pad may be less during electroplating than during electroetching.

Description

technical field [0001] This invention relates to semiconductor processing, and more particularly to methods and apparatus for electroplating and planarizing copper layers on semiconductor wafers. Background technique [0002] Deposition and selective removal of metal layers are important processes in semiconductor device fabrication. A typical semiconductor wafer has several layers of metal deposited or plated on its surface, each successive layer being polished or etched before additional layers are added. In general, electroplating copper on wafer surfaces is an extensively skilled process. Chemical-mechanical polishing (CMP) is usually performed after copper electroplating (usually a capping layer of copper is produced on the wafer) to remove unwanted portions of the electroplating. When fabricating damascene structures, the CMP process can also be used to electrically isolate damascene wiring. [0003] Figure 1A is a schematic diagram of a typical apparatus for electr...

Claims

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Application Information

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IPC IPC(8): C25D5/48C25D7/12H01L21/288H01L21/321H01L21/768
CPCY10S205/917C25D5/48C25D7/123H01L21/3212H01L21/2885H01L21/7684C25D17/001C25D7/12H01L21/32125C25D17/00C25D5/611
Inventor L·埃科诺米可斯H·德利吉安尼J·M·科特H·J·格拉巴尔兹B·陈
Owner GLOBALFOUNDRIES INC
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