Programmable asynchronous triggering time delayer, and method of use
A trigger and delay technology
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[0016] The circuit structure of the programmable asynchronous trigger delay device of the present invention is as follows: figure 2 As shown, it includes n T' flip-flops, the n T' flip-flops are connected one by one, the output terminal of the previous T' flip-flop is connected to the CLK terminal of the next T' flip-flop, and the first T' flip-flop is connected to the CLK terminal of the next T' flip-flop. The CLK terminal of the 'flip-flop is connected to the external clock pulse, the SET terminal and the RST terminal of these T' flip-flops are count value input terminals, from the first T' flip-flop to the nth T' flip-flop corresponding to the input binary From the lowest bit to the highest bit of the data, the present invention also includes the n+1th T' flip-flop, the CLK terminal of the T' flip-flop is connected to the output end of the nth T' flip-flop, and the output of the T' flip-flop The terminal is the output terminal of the delay signal, and the number n of the T...
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