Method and circuitry for preserving a logic state

Abstract

In response to a first transition of a clock signal, an information signal having a logic state is received. In response to a second transition of the clock signal, first circuitry latches a logic state of a first signal that indicates the information signal's logic state. In response to a third transition of the clock signal, second circuitry latches a logic state of a second signal that indicates the first signal's logic state. During a first mode of operation, power is supplied to the first and second circuitry. During a second mode of operation, power is reduced to the first circuitry, while power is supplied to the second circuitry, so that the first signal's logic state is lost, while the second signal's logic state is preserved.

Description

technical field [0001] The present invention relates generally to information handling systems, and more particularly to methods and circuits for preserving logic states. Background technique [0002] In circuits for selectively latching logic states (eg, binary 0 or 1), it is desirable to reduce energy consumption especially during inactive periods (eg, when the logic state is static). A disadvantage of one prior art technique for reducing energy consumption is that the performance (eg, speed) of the circuit is reduced during active operation. In another prior art technique, the performance of the circuit is maintained during active operation, but the logic state is either (a) not preserved during inactivity; The inefficient way of restoring logic state during reset processing is saved. [0003] Therefore, there is a need for a method and circuit for storing logic states, which can overcome various shortcomings of the prior art. For example, there is a need for a method ...

AI Technical Summary

Problems solved by technology

A disadvantage of a prior art technique for reducing energy consumption is that the performance (eg, speed) of the circuit is reduced during active operation

In another prior art technique, the performance of a circuit is preserved during active operation, but the logic state is either (a) not preserved during inactivity; way of restoring logic state during inefficient reset handling is saved

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