Deep structure forming method

Abstract

The invention relates to a deep junction structure. A self-aligned high-energy implantation process of forming a deep junction structure. For exposing a predetermined region of a semiconductor substrate, a masking structure has a gate layer, a hard mask layer patterned on the gate layer, and a photoresist layer covering parts of said semiconductor substrate, said gate layer and said hard mask layer. The hard mask layer has a thickness greater than 350 Angstroms. Using the masking structure and performing an ion implantation process requiring an energy greater than 70 keV, a doped region of a second conductive type is formed in the predetermined region of the semiconductor substrate of a first conductive type.

Description

technical field [0001] The invention relates to a semiconductor manufacturing method, in particular to a self-alignment high-energy implantation process for forming a deep junction structure in a semiconductor substrate. Background technique [0002] The high-energy implantation process is very important for forming a doped layer deep in the substrate or forming a doped layer in the substrate through an overlying thick film. For CMOS image sensor technology in VLSI applications, the high-energy implantation process is also a key technology to form a deep junction structure between the p-type and n-type diffusion regions (as photodiode regions). The high-energy implantation process also helps to form n-type wells or p-type wells after the high-temperature step of field oxidation, such as effectively suppressing lateral diffusion and reducing the required well layout. The high-energy implant process can also be used to replace the buried layers of conventional random access m...

AI Technical Summary

Problems solved by technology

However, when the high-energy implant energy is greater than 40keV and increases to several MeV, the polysilicon gate mask is no longer effective, because the dopant will penetrate through the polysilicon gate mask and affect the device performance, such as channel length, thereby enlarging the device size and reduce transistor density

The above problems will become more serious when the thickness of the polysilicon gate layer is reduced due to the shrinking device size

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