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Chip packing structure and method

A technology of chip encapsulation and encapsulation method, which is applied in the manufacture of electrical components, electrical solid-state devices, semiconductor/solid-state devices, etc., and can solve problems such as the influence of reliability of electronic components

Inactive Publication Date: 2007-01-17
BOARDTEK ELECTRONICS CORP
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  • Abstract
  • Description
  • Claims
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AI Technical Summary

Problems solved by technology

[0004] And at present, when making a circuit board, each component is welded on the circuit board one by one, so when an electronic component is produced, the coplanarity of the entire circuit board surface has a considerable influence on the reliability of the electronic component

Method used

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  • Chip packing structure and method
  • Chip packing structure and method

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Embodiment Construction

[0021] The chip packaging method proposed by the present invention and the package structure produced by it will be described below through different embodiments.

[0022] Figure 1(a) to Figure 1(h) Shown is the cross-sectional view of each step of the packaging method of the chip packaging structure of the present invention. First, as shown in FIG. An adhesive layer 22 and a conductive layer 24 are sequentially arranged on the surface from bottom to top, wherein the carrier board 20, the adhesive layer 22 and the conductive layer 24 can be integrated into a commercialized structure, or can be divided into three steps. , first use the pasting method, printing, spin coating, sputtering method, electroless plating method or electroplating method, such as the sputtering method to set the adhesive layer 22 on the carrier plate 20, and then use the pasting method, printing, sputtering method, The electroless plating method or the electroplating method disposes the conductive layer...

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Abstract

A wafer sealing structure and the sealing method: sets the adhere layer, the conducting layer and the metal layer on the panel in turn, forms the perforative design groove on the conducting layer and the metal layer, divides the metal layer into one or several wafer loading areas and several conducting point areas that is isolation or connection with each other, forms a wafer on every wafer loading area, wafer electric connect with the conducting point area, uses the sealing colloid to cover on the conducting layer, the metal layer and the wafer, removes the loading board, processes incision that every wafer or the wafer group is as the unit, forms several wafer sealing structures. The invention can improve the trustiness of the sealing process, and reduce the height of the seal.

Description

technical field [0001] The invention relates to a chip package structure and a package method thereof, in particular to a relatively flat chip package structure with a low package height and a package method thereof. Background technique [0002] With the rapid improvement of the functions of products such as computers and network communications, semiconductor technology must have the requirements of diversification, portability, and miniaturization, so that the chip packaging process industry can break away from traditional technologies and move towards high power, high density, light, and thin In addition to the development of high-precision processes such as miniaturization, electronic packaging (ElectronicsPackaging) needs to have high reliability, good heat dissipation and other characteristics to transmit signals and electric energy, as well as provide good heat dissipation and structural protection. support etc. [0003] It has become a trend to manufacture small-siz...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/50H01L23/48
CPCH01L24/97H01L2224/48091H01L2224/48247
Inventor 郑先锋
Owner BOARDTEK ELECTRONICS CORP
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