Semiconductor package structure and manufacturing method thereof

Abstract

The present invention proposes a semiconductor packaging structure, which is characterized in that the semiconductor packaging structure includes: a main body substrate, including an upper surface circuit, a lower surface circuit, and a side surface connecting the upper surface circuit and the lower surface circuit, and the upper surface The circuit is electrically connected to the circuit on the lower surface; the chip includes a first connecting surface and a second connecting surface oppositely arranged, and the first connecting surface is electrically connected to the circuit on the lower surface; the plastic sealing layer completely covers the The side surface of the substrate, and the plastic encapsulation layer at least partially covers the lower surface circuit and the chip; the back gold layer includes at least one first metal connection part connected to the second connection surface of the chip, the first The metal connection part includes an extension surface extending and protruding out of the plastic sealing layer, and the sum of the areas of the extension surfaces is greater than the area of ​​the second connection surface. The invention solves the heat dissipation problem of the chip while reducing the production cost, and meets and exceeds the requirement of level 3 moisture sensitivity of the packaging body.

Description

technical field [0001] The invention belongs to the field of semiconductor manufacturing, and in particular relates to a semiconductor packaging structure and a manufacturing method thereof. Background technique [0002] In the existing chip packaging structure, due to the heat dissipation requirements of the control chip and the package body, metal (back gold) is generally deposited on the back of the chip to reduce thermal resistance. [0003] At the same time, for large chips with high heat dissipation requirements, it is currently mainly carried out by direct back gold deposition and molding on the wafer. However, using this method to dissipate heat, if it is necessary to back gold on a wafer with a thickness of less than 180um after thinning, it needs to be supported by expensive temporary bonding. At the same time, another solution is to use substrate-embedded chips, but there are also serious yield problems. [0004] The above two heat dissipation structures and met...

AI Technical Summary

Problems solved by technology

However, using this method to dissipate heat, if it is necessary to back gold on a wafer with a thickness less than 180um after thinning, it needs to be supported by expensive temporary bonding.

At the same time, another solution is to use substrate-embedded chips, but there are also serious yield problems

[0004] The above two heat dissipation structures and methods may have the problem of substrate exposure, and the reliability of the package structure is relatively low, and generally cannot pass the requirements of moisture sensitivity level 1 (MSL1), making the package body susceptible to moisture

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