Semiconductor memory and method for manufacturing the same

Abstract

The present invention provides a semiconductor memory which has high reliability and can prevent the Vt alteration caused by the UV light generated in the fabricating process of the semiconductor memory and method for manufacturing the same. An interlayer insulating film (106) is formed over the memory cells (100) and bit line contact plugs (109) are formed in the interlayer insulating film to be connected to the bit lines (102). The semiconductor memory includes: bit lines (102) made of a diffusion layer formed in a semiconductor substrate (101), charge-trapping gate insulating films formed between the bit lines (102) and word lines (104) formed on the gate insulating films. Further, a light blocking film (105) is formed on at least part of the interlayer insulating film covering the memory cells (105) and part of the light blocking film (105) formed on the interlayer insulating film extends from the surface to the inside of the interlayer insulating film (106) in the neighborhood of the bit line contact plugs (109).

Description

technical field [0001] The present invention relates to a semiconductor memory device including a nonvolatile memory having a trapping gate insulating film and a method of manufacturing the same. Background technique [0002] As an electrically writable nonvolatile memory, there is known a memory structure in which a wiring layer composed of a diffusion layer doubles as a source and a drain of a memory transistor (virtual ground system). [0003] In recent years, there have been increasing demands for ultra-miniaturization, high integration, high performance, and high reliability of semiconductor devices. In particular, high reliability is very important for small nonvolatile memories. [0004] FIG. 26 is a diagram showing a general structure of a memory cell 200 having a trapping gate insulating film. The memory cell 200 includes a bit line 202 formed of a diffusion layer formed on a semiconductor substrate 201 , a bit line oxide film 210 , a trapping gate insulating film ...

AI Technical Summary

Problems solved by technology

[0031] As is well known, the bit line contact pillar 209 is formed on the bit line extended to the periphery of the memory cells arranged in an array, but since the opening area of ​​the contact hole 215 is very small, when the contact hole is formed, no consideration is given to via the contact hole. Aperture 215, UV light intrusion into the vicinity of the memory cell

[0032] However, if the miniaturization and thinning of the memory cell further progress toward a lower Vt, it is considered that the intensity of the UV light entering through the above-mentioned path becomes non-negligible, and as a result, the Vt of the memory cell near the bit line contact post 209 rises. high

However, in the existing semiconductor memory device, only the UV light generated in the wiring manufacturing process formed on the memory cell is specifically considered, and the UV light invading through the bit line contact hole 215 is not considered.

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