Semiconductor device and manufacturing method therefor
A semiconductor, one-way technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as increase and decrease of parasitic resistance, and achieve the effect of suppressing inter-band tunneling current
- Summary
- Abstract
- Description
- Claims
- Application Information
AI Technical Summary
Problems solved by technology
Method used
Image
Examples
no. 1 Embodiment approach
[0047] The first embodiment of the present invention provides a field effect transistor. FIG. 1 is a partial vertical cross-sectional view showing the structure of a transistor according to a first embodiment of the present invention. FIG. 2 is a partially enlarged vertical sectional view showing the electric field near the gate of the transistor shown in FIG. 1. FIG.
[0048] (structure)
[0049] As shown in FIG. 1, the field effect transistor of the first embodiment of the present invention is provided on a silicon substrate 1. Specifically, the field oxide film 2 is selectively provided on the silicon substrate 1. The field oxide film 2 defines the active area on the silicon substrate 1. In this active region, a P-type well 4 is provided. The field effect transistor is provided on the P-type well 4. The field effect transistor includes: a gate insulating film 3; a gate structure provided on the gate insulating film 3; first and second sidewall structures provided on both sidewa...
Deformed example 1
[0124] The field-effect transistor is formed in a P-type well 4, which is selectively formed on the silicon substrate 1. However, for example, it may also be formed in an SSRW (Super Steep Retrograde Well). The SSRW is selectively formed on the silicon substrate 1. 9 is a partial vertical cross-sectional view showing the structure of a transistor according to a first modification of the first embodiment of the present invention. A normal well has a substantially uniform impurity concentration, but by forming an SSRW (Super Steep Retrograde Well) 16, the interface region 16-1 with the gate insulating film 3 is drastically reduced to 1E17[ l / cm 3 ], the impurity concentration in regions other than this is 1E18[l / cm 3 ]. By using this structure, the on-resistance of the transistor is reduced, and the driving capability can be improved. The manufacturing method of the SSRW (Super Steep Retrograde Well) 16 is well-known, so the description is omitted here.
Deformed example 2
[0126] The field-effect transistor is formed in a P-type well 4, which is selectively formed on a silicon substrate 1, but may also be formed on an SOI (Silicon-On-Insulator) substrate. on. 10 is a partial vertical cross-sectional view showing the structure of a transistor according to a second modification of the first embodiment of the present invention. An oxide film 17 buried in the silicon substrate 1 is provided, and an SOI (Silicon-On-Insulator) film 18 made of silicon is provided on the buried oxide film 17. The field effect transistor is formed on the SOI (Silicon-On-Insulator) film 18. The manufacturing method of the SOI substrate is well-known, so the description is omitted here.
PUM
Login to View More Abstract
Description
Claims
Application Information
Login to View More 