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Semiconductor device and manufacturing method therefor

A semiconductor, one-way technology, applied in semiconductor/solid-state device manufacturing, semiconductor devices, electrical components, etc., can solve problems such as increase and decrease of parasitic resistance, and achieve the effect of suppressing inter-band tunneling current

Inactive Publication Date: 2007-06-13
OKI ELECTRIC IND CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, if the impurity concentration is lowered, the parasitic resistance between source and drain increases

Method used

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  • Semiconductor device and manufacturing method therefor
  • Semiconductor device and manufacturing method therefor
  • Semiconductor device and manufacturing method therefor

Examples

Experimental program
Comparison scheme
Effect test

no. 1 Embodiment approach

[0047] The first embodiment of the present invention provides a field effect transistor. FIG. 1 is a partial vertical cross-sectional view showing the structure of a transistor according to a first embodiment of the present invention. FIG. 2 is a partially enlarged vertical sectional view showing the electric field near the gate of the transistor shown in FIG. 1. FIG.

[0048] (structure)

[0049] As shown in FIG. 1, the field effect transistor of the first embodiment of the present invention is provided on a silicon substrate 1. Specifically, the field oxide film 2 is selectively provided on the silicon substrate 1. The field oxide film 2 defines the active area on the silicon substrate 1. In this active region, a P-type well 4 is provided. The field effect transistor is provided on the P-type well 4. The field effect transistor includes: a gate insulating film 3; a gate structure provided on the gate insulating film 3; first and second sidewall structures provided on both sidewa...

Deformed example 1

[0124] The field-effect transistor is formed in a P-type well 4, which is selectively formed on the silicon substrate 1. However, for example, it may also be formed in an SSRW (Super Steep Retrograde Well). The SSRW is selectively formed on the silicon substrate 1. 9 is a partial vertical cross-sectional view showing the structure of a transistor according to a first modification of the first embodiment of the present invention. A normal well has a substantially uniform impurity concentration, but by forming an SSRW (Super Steep Retrograde Well) 16, the interface region 16-1 with the gate insulating film 3 is drastically reduced to 1E17[ l / cm 3 ], the impurity concentration in regions other than this is 1E18[l / cm 3 ]. By using this structure, the on-resistance of the transistor is reduced, and the driving capability can be improved. The manufacturing method of the SSRW (Super Steep Retrograde Well) 16 is well-known, so the description is omitted here.

Deformed example 2

[0126] The field-effect transistor is formed in a P-type well 4, which is selectively formed on a silicon substrate 1, but may also be formed on an SOI (Silicon-On-Insulator) substrate. on. 10 is a partial vertical cross-sectional view showing the structure of a transistor according to a second modification of the first embodiment of the present invention. An oxide film 17 buried in the silicon substrate 1 is provided, and an SOI (Silicon-On-Insulator) film 18 made of silicon is provided on the buried oxide film 17. The field effect transistor is formed on the SOI (Silicon-On-Insulator) film 18. The manufacturing method of the SOI substrate is well-known, so the description is omitted here.

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PUM

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Abstract

A semiconductor device of the present invention includes a source region, a drain region, a gate having a first sidewall, a first insulating sidewall structure disposed to contact the first sidewall of the gate, and a first conductive sidewall structure that is electrically isolated from the gate through the first insulating sidewall structure and electrically coupled to a first region that is one of the source region or the drain region. According to this semiconductor device, the first conductive sidewall structure has an electric potential that is substantially the same as that of the first region. Therefore, steep band bending is not generated in a portion of the first region that is disposed in the vicinity of a gate insulation film. Because of this, the first sidewall structure makes it possible to inhibit the band-to-band tunneling current.

Description

Technical field [0001] The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a field effect transistor having an effective structure for suppressing off-leak current caused by tunneling current between bands, and a manufacturing method thereof. Background technique [0002] Field effect transistors represented by MISFETs and MOSFETs are integrated on semiconductor integrated circuits such as LSI. In order to achieve an increase in the integration level of semiconductor integrated circuits, an increase in operating speed, and a reduction in power consumption, field-effect transistors are required to be miniaturized. Then, with this miniaturization, the film thickness of the gate insulating film of the field effect transistor becomes thinner, and the depth of the source / drain junction also becomes shallow. [0003] For example, Patent Document 1 discloses a field-effect transistor having a main gate made of metal or met...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L29/78H01L29/41
CPCH01L29/7833H01L29/41783H01L29/4983H01L21/26586H01L29/1083H01L29/6656H01L29/66484H01L29/41775H01L29/665H01L29/402H01L29/78654H01L29/7831H01L29/66772H01L21/18
Inventor 福田浩一
Owner OKI ELECTRIC IND CO LTD