Processor unit efficiency control

Abstract

Embodiments provide for a computer implemented method comprising sampling one or more power and performance metrics of a processor; determining an energy cost per instruction based on the one or more power and performance metrics; determining an efficiency metric based on the energy cost per instruction; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor.

Description

CROSS-REFERENCE[0001]The present application is a non-provisional application claiming the benefit of U.S. Provisional Application No. 62 / 348,293 filed on Jun. 10, 2016, which is hereby incorporated herein by reference.BACKGROUND OF THE DISCLOSURE[0002]Processors may use performance control logic to dynamically vary the frequency and voltage of a processor or processor core based on the computational demands placed on the processor. This can be particularly of use in battery-operated systems where minimizing power consumption is important for enabling extended use. In general, performance control logic operates by monitoring the operational state of the processor and dynamically adjusting the voltage and clock frequency of the processor to provide increased performance under high computational loads and reduced power consumption under minimal load or idle conditions. However, increasing the performance of a processor may result in reduced system efficiency and battery life. Moreover...

AI Technical Summary

Benefits of technology

[0004]One embodiment provides for a computer implemented method comprising sampling one or more power and performance metrics of a processor; determining an energy cost per instruction based on the one or more power and performance metrics; determining an efficiency metric based on the energy cost per instruction; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor.

[0005]One embodiment provides for a non-transitory machine-readable medium storing instructions which, when executed by a processor complex including one or more processors, cause the processor complex to perform operations comprising determining an efficiency metric based on an energy cost per instruction of one or more processors of the processor complex; computing an efficiency control error based on a difference between a current efficiency metric and a target efficiency metric; setting an efficiency control effort based on the efficiency control error; determining a performance control effort, the performance control effort determined by a performance controller for the processor complex; and adjusting the performance control effort based on the efficiency control effort, wherein adjusting the performance control effort reduces power consumption of the processor complex.

Problems solved by technology

However, increasing the performance of a processor may result in reduced system efficiency and battery life.

Moreover, the increased processor performance may result in a significantly higher thermal load on the processor or other components within an electronic device that incorporates the processor.

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