Application of duty cycle correction to a level shifter via a feedback common mode resistor

Abstract

Systems, apparatuses, and methods for applying duty cycle correction to a level shifter via a feedback common mode resistor are disclosed. A circuit includes a capacitor, an inverter, and at least one feedback resistor. An input signal is received and coupled through the capacitor to the inverter. To correct for duty cycle distortion on the input signal, a duty cycle correction signal is applied to the at least one feedback resistor in the feedback path. The duty cycle correction signal can be applied as a voltage or as a current. In one implementation, the location of the injection point for applying the duty cycle correction signal within the at least one feedback resistor is programmable.

Description

BACKGROUNDDescription of the Related Art[0001]Modern semiconductor chips include a variety of circuits and components to facilitate fast and efficient computation. When transferring information between functional blocks in a semiconductor chip, electrical signals are typically sent on metal traces. Transmitters in a first functional block send the electrical signals across the metal traces. Receivers in a second functional block receive the electrical signals. In some cases, the two functional blocks are within a same die. In other cases, the two functional blocks are on separate dies.[0002]The processing speed of information processing systems and devices continues to increase as new systems and devices are developed. Additionally, for high-speed signal transmission, signals are often transmitted at low amplitude levels. Circuits for transmitting high-speed signals can exhibit variations in duty cycle caused by variations in manufacturing process, operating voltage, temperature, or...

AI Technical Summary

Benefits of technology

The patent text describes methods and mechanisms for correcting duty cycle distortion in high-speed signal transmission. The technical effects of the patent include improving the accuracy of clock timing and ensuring the proper transfer of data between components. The methods and mechanisms involve applying a duty cycle correction value to a level shifter via a feedback common mode resistor, which can be programmed to correct for duty cycle distortion. The patent also describes the implementation of a circuit for applying duty cycle correction to a level shifter via a feedback common mode resistor, as well as the use of a non-transitory computer-readable storage medium and the injection point of the duty cycle correction signal. Overall, the patent provides solutions for ensuring the reliable and efficient transfer of information in high-speed devices.

Problems solved by technology

If the clock duty cycle is not 50% or within some margin of 50%, the timing between the rising and falling edges can be distorted, causing data to be clocked in or out of the memory at incorrect times. For high-speed, low-amplitude signals, correcting for duty cycle distortion can be challenging.

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