Methods and media for utilizing symbolic expressions in circuit modules

Abstract

The invention provides parametric modules called Self Implementing Modules (SIMs) for use in programmable logic devices such as FPGAs. The invention further provides tools and methods for generating and using SIMs. SIMs implement themselves at the time the design is elaborated, targeting a specified FPGA according to specified parameters that may, for example, include the required timing, data width, number of taps for a FIR filter, and so forth. In one embodiment, the SIM parameters may be symbolic expressions, which may comprise strings or string expressions, logical (Boolean) expressions, or a combination of these data types. The variables in these expressions are either parameters of the SIM or parameters of the "parent" of the SIM. Parametric expressions are parsed and evaluated at the time the SIM is elaborated; i.e., at run-time, usually when the design is mapped, placed, and routed in a specific FPGA. The use of parametric expressions interpreted at elaboration time allows dynamic inheritance and synthesis of actual parameter values, rather than the static value inheritance commonly found in programming languages such as C++ and Java.

Description

[0001] This application is a continuation application of commonly assigned, co-pending U.S. patent application Ser. No. 09 / 049,518, entitled "FPGA MODULES PARAMETERIZED BY EXPRESSIONS", invented by Sundararajarao Mohan et al. and filed Mar. 27, 1998, which is incorporated herein by reference.[0002] This application further relates to commonly assigned, copending U.S. patent application Ser. No. 09 / 049,598, entitled "METHOD FOR CONSTRAINING CIRCUIT ELEMENT POSITIONS IN STRUCTURED LAYOUTS", invented by Cameron D. Patterson et al. and filed Mar. 27, 1998, which is incorporated herein by reference.[0003] 1. Field of the Invention[0004] The invention relates to programmable integrated circuits (ICs). More particularly, the invention relates to parametric logic modules for implementing designs in programmable ICs, and software tools and methods for creating such modules.[0005] 2. Description of the Background Art[0006] Programmable ICs are a well-known type of digital integrated circuit t...

AI Technical Summary

Benefits of technology

[0027] SIMs can be hierarchical, i.e., they can include other SIMs, thereby forming a logical hierarchy. In addition, SIMs can include a separate physical hierarchy which is imposed in addition to the logical hierarchy. SIMs therefore offer the advantages of hierarchical design. In some embodiments, SIM parameters are passed down through the hierarchy from a given "parent" SIM to its sub-SIMs, or "children".

[0030] Because SIMs are preferably implemented using object-oriented software, they are easy both to use and to design. The computer code devices in a SIM may, however, be any interpreted or executable code mechanism, such as scripts, interpreters, dynamic link libraries, Java.TM. classes, and complete executable programs. (Java is a trademark of Sun Microsystems, Inc.) In one embodiment, all information for the SIM is included in a single Java object, which may reference other Java objects.

[0032] SIMS are easily delivered over a data communications link such as the internet. Therefore, in one embodiment a SIM is protected from duplication or alteration by providing an encrypted SIM that requires a key to decrypt the SIM, using well-known techniques.Modules Parameterized by Expressions

[0040] In one embodiment, the user can specify a plurality of floorplanners to be applied to different portions of a single FPGA. Where more than one floorplanner is present in a design, the floorplanners may be active simultaneously, and may communicate with each other to implement the SIMs in a fashion that leads to the most desirable overall solution. The most desirable solution is determined by the user, who specifies timing and spatial requirements using known methods such as attaching parameters to a module or setting software options. The ability to run multiple floorplanners simultaneously speeds up the implementation process, due to the parallel processing of the placement task. In other words, this embodiment applies the well-known "divide-and-conquer" strategy to physical layout of an FPGA design.

Problems solved by technology

As FPGA designs increase in complexity, they reach a point at which the designer cannot deal with the entire design at the gate level.

True hierarchical design is difficult to achieve for FPGAs using currently-available software.

Designs can be entered hierarchically (e.g., via schematic entry or Hardware Description Languages (HDLs)), but mapping, placement and routing software typically "flattens" the design.

The netlist was encrypted and sent to customers in binary format, which made it difficult to edit or reverse-engineer the netlist.

One disadvantage of the hard macro format was that the area of the FPGA encompassed by the hard macro was totally dedicated to the contents of the macro.

If the logic fit best, or resulted in the fastest performance, in a non-rectangular area, the extra CLBs required to make the area rectangular were wasted.

Therefore, libraries of RPMs are typically large and limited in scope.

The design as a whole can therefore utilize a non-uniform global placement strategy, a technique that is not practical using prior art methods.

While the interconnect fabric of any large FPGA is homogeneous in that it follows a predefined pattern, the interconnect structure typically cannot be segmented into large minimally interacting areas.

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