Nonvolatile semiconductor memory device

Abstract

A nonvolatile semiconductor memory device is disclosed, which comprises a memory cell portion including at least one memory cell configured to store n levels (n is 3 or more), a bit line connected to one end of the memory cell portion, a data input / output circuit, and a data circuit which is connected to the bit line and the input / output circuit and configured to store write data or read data of 2 bits or more into or from the memory cell portion, in which, during a write operation, the write data inputted from the data input / output circuit is held in the data circuit and the read data read from the memory cell is held on the bit line.

Description

[0001] This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-119659, filed Apr. 18, 2001 the entire contents of which are incorporated herein by reference.[0002] 1. Field of the Invention[0003] The present invention relates to a nonvolatile semiconductor memory device, particularly to a multi-level or multi-value NAND cell type EEPROM device (electrically erasable and programmable read only memory) such as a four-level NAND cell type EEPROM device.[0004] 2. Description of the Related Art[0005] As one of nonvolatile semiconductor memories, a NAND cell type EEPROM device is known. The EEPROM device has a memory cell array constituted of a plurality of NAND cell units. Each NAND cell unit is connected between a bit line and a source line and is constituted of a plurality of memory cells connected in series to one another and two select transistors connected to ends of the series-connected memory cells.[0006] Each memory ce...

AI Technical Summary

Problems solved by technology

Therefore, a sufficient high voltage for erasing the data is not applied between the control gate electrodes and the well region in the memory cells in the unselected block.

Therefore, when the data stored in the memory cell is multi-level (n-level) and the value of n increases, then the number of latch circuits in a memory chip increases and thus a chip area disadvantageously increases.

However, even the constitution proposed as described above cannot necessarily sufficiently solve the problem that the number of elements in the data circuit increases and the chip area increases.

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