Conditional clock buffer circuit

Abstract

A conditional clock buffer circuit includes a clock output and is coupled to receive a clock input and a condition signal. The conditional clock buffer circuit includes a first circuit coupled to receive the clock input and a second circuit coupled to receive the clock input and the condition signal. The first circuit is configured to generate a first state on the clock output responsive to a first phase of the clock input. The second circuit is configured to conditionally generate a second state on the clock output responsive to the condition signal during a first portion of a second phase of the clock input. In one implementation, one or more of the conditional clock buffer circuits may be included in a clock tree. The clock tree may also include one or more levels of buffering.

Description

[0001] 1. Field of the Invention[0002] This invention is related to the field of conditional clock buffer circuits.[0003] 2. Description of the Related Art[0004] As electronic circuits increase in density, particularly integrated circuits, power consumption has also increased. In order to minimize power consumption, power management circuitry may be used. Power management circuitry may be used to selectively and / or temporarily remove power from a certain part of an electronic circuit during times while that part is inactive. Alternatively or in addition, conditional clocking schemes may be used.[0005] Conditional clocking may be used to conditionally generate a clock to a functional circuit dependent on whether or not the functional circuit is active. If the circuit is active, the clock is generated (e.g. rising and falling edges are generated providing a high phase and a low phase of the clock signal). If the circuit is inactive, the clock may be inhibited (e.g. held in a constant ...

AI Technical Summary

Problems solved by technology

As electronic circuits increase in density, particularly integrated circuits, power consumption has also increased.

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