Bit line contact structure and fabrication method thereof

Abstract

A bit line contact structure and fabrication method thereof. The method includes providing a substrate having a transistor, with a gate electrode, drain region, and source region, on the substrate, blanketly forming a first dielectric layer on the transistor using spin coating, and patterning the first dielectric layer, forming a via exposing the drain region.

Description

BACKGROUND OF THE INVENTION [0001] 1. Field of the Invention [0002] The present invention relates to a bit line contact structure and fabrication method thereof, and more specifically to a bit line contact structure using a spin-coating material as a pre-metal dielectric layer. [0003] 2. Description of the Related Art [0004] As the integrity of integrated circuits increases, the size of semiconductor device is reduced. A dynamic random access memory (DRAM) device, for example, has a design rule for 64 MB DRAM of 0.3 μm or less, with design rule of 128 MB and 256 MB as low as 0.2 μm or less. [0005] In a bit line contact structure, for example, when the line width is reduced to approximately 0.11 μm, the width of a drain region exposed by a bit line contact via is also reduced. When forming a conductive layer as bit line contact (CB) in the bit line contact via, either CB opening or word line-bit line shorts occur frequently, resulting in device failure, negatively affecting the yield...

AI Technical Summary

Benefits of technology

[0021] Thus, objects of the present invention are to provide a bit line contact structure and fabrication method thereof, avoiding bit line-bit line short, CB opening, and word line-bit line short in the process in order to improve process yield and decrease costs.

Problems solved by technology

When forming a conductive layer as bit line contact (CB) in the bit line contact via, either CB opening or word line-bit line shorts occur frequently, resulting in device failure, negatively affecting the yield and cost of the process.

The hole-filling capability of BPSG is insufficient to prevent voids in BPSG used as the PMD layer, further negatively affecting the yield and cost of the process.

Thus, bit line-bit line shorts occur, negatively affecting the yield and cost of the process.

Thus, word line-bit line short occurs, negatively affecting the yield and cost of the process.

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