Configurable embedded processor

Abstract

A microprocessor system includes a multi-bank memory having a first memory bank and a second memory bank, a muxing circuit, a CPU and a DMA controller. The muxing circuit allows the CPU to access one of the memory bank while allowing the DMA controller access to the other memory bank at the same time. Thus, the microprocessor system needs to process multiple data sets, the CPU can be processing a first data set in the first memory bank while the DMA controller is writing a second data set in the second memory bank. When the CPU is finished processing the first data set and the DMA controller is finished writing the second data set, the muxing circuit is reconfigured so that the CPU can process the second data set in the second memory bank and the DMA controller can write a third data set in the first memory bank.

Description

FIELD OF THE INVENTION [0001] The present invention relates to microprocessor systems, and more particularly to a memory system for a microprocessor system to reduce memory contention between a CPU and a DMA controller. BACKGROUND OF THE INVENTION [0002]FIG. 1(a) illustrates a conventional microprocessor system 100 having a central processing unit (CPU) 110, a direct memory access (DMA) controller 120, a single port memory 130 and a memory bus 140. CPU 110 and DMA controller 120 are coupled to single port memory 130 by memory bus 140. In general both CPU 110 and DMA controller 120 are memory access devices that are considered bus master, while single port memory 130 is considered a slave device that is being shared by the bus masters. [0003] In many situations, particularly for digital signal processing, DMA controller 120 must store a data set in single port memory 130 for CPU 110 to process. Ideally, DMA controller 120 would store a second data set for CPU 110 after writing the fi...

AI Technical Summary

Benefits of technology

[0008] Accordingly, a microprocessor system in accordance with the present invention, uses multiple single port memory banks to allow efficient use of the CPU and the DMA controller as well as other bus masters. For example, in one embodiment of the present invention, as the CPU is processing a first data set in the first memory bank, the DMA controller can be writing a second data set into the second memory bank. Once the CPU is finished processing the first data set and the DMA controller has finished writing the second data set, the CPU can process the second data set in the second memory bank while the DMA controller writes a third data set into the first memory bank. By using the memory banks in parallel, the present invention provides higher utilization of the CPU and the DMA controller.

Problems solved by technology

Furthermore, dual port memories have much higher power consumption and operate at lower frequencies than single port memories.

In addition dual port memories have additional complexities such as port contention for the same memory addresses that must be resolved.

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