Semiconductor integrated circuit

a technology of integrated circuits and semiconductors, applied in the direction of semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of more malfunctions in the semiconductor integrated circuit, the power supply potential of the data circuit 620 is varied, and the clock jitter degradation, so as to prevent the clock signal wiring from being affected and the amount of clock signal jitter caused by crosstalk noise reduction

Inactive Publication Date: 2006-12-07
PANASONIC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0033] Then, it is possible to prevent the clock signal wiring from being affected by crosstalk noise produced when a signal change occurs in the data signal wiring, whereby the amount of jitter in the clock signal caused by the crosstalk noise can be reduced.

Problems solved by technology

However, when the data circuits 620 operate in synchronization with the input clock signal and thereby consume power, the power supply potential of the data circuits 620 is varied to produce power supply noise.
As a result, the amount of variation in the delay time of the transistors in the clock circuits 630 varies from one clock cycle to another, which causes degradation of the clock jitter.
For example, a failure to latch data (which will be hereinafter referred to as “data mislatch”) due to the degradation of the clock jitter is more likely to occur, causing more malfunctions in the semiconductor integrated circuit.

Method used

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  • Semiconductor integrated circuit
  • Semiconductor integrated circuit
  • Semiconductor integrated circuit

Examples

Experimental program
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first embodiment

of the Present Invention

[0042]FIG. 1 is a block diagram showing the structure of a semiconductor integrated circuit 100 according to a first embodiment of the present invention. As shown in the figure, the substrate of the semiconductor integrated circuit 100 includes a data cell region 110 and a clock cell region 120, in which circuits are formed.

[0043] The data cell region 110 includes data circuits 111 and data circuit power supply wiring 112.

[0044] The data circuits 111 are composed of buffers, logic gates, flip flops, or the like and perform signal processing of an input signal.

[0045] The data circuit power supply wiring 112 provides the data circuits 111 with power supply voltage.

[0046] The clock cell region 120 includes clock circuits 121 and clock circuit power supply wiring 122.

[0047] The clock circuits 121 are composed of buffers, logic gates, flip flops, or the like and supply an input clock signal to the data cell region 110.

[0048] The clock circuit power supply wi...

second embodiment

of the Present Invention

[0066]FIG. 3 is a block diagram showing the structure of a semiconductor integrated circuit 200 according to a second embodiment of the present invention. In the below-described embodiments, the components having the same function as those of the first embodiment and the like are designated by the same reference numerals and the description thereof will be thus omitted herein.

[0067] The semiconductor integrated circuit 200 is different from the semiconductor integrated circuit 100 of the first embodiment in that the data circuit power supply wiring 112 and the clock circuit power supply wiring 122 are connected with each other by a coil 270 instead of by the vias 170.

[0068] The coil 270 is an impedance element and a feature of the coil 270 is that the resistance component thereof is zero while the reactance component thereof has a finite value. It is well known that the resistance component of an impedance element typically causes a voltage drop for the dir...

third embodiment

of the Present Invention

[0076]FIG. 4 is a block diagram showing the structure of a semiconductor integrated circuit 300 according to a third embodiment of the present invention. The semiconductor integrated circuit 300 includes a data cell region 110, a first clock cell region 310, and a second clock cell region 320.

[0077] The semiconductor integrated circuit of this embodiment is different from the semiconductor integrated circuit of the first embodiment in that two clock signals are input into the semiconductor integrated circuit 300 through a first clock input terminal 330 and a second clock input terminal 340 and that the clock signal input through the first clock input terminal 330 is propagated by clock circuits 121 included in the first clock cell region 310 so as to be input into corresponding data circuits 111 in the data cell region 110 and the clock signal input through the second clock input terminal 340 is propagated by clock circuits 121 included in the second clock c...

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PUM

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Abstract

Data circuit power supply wiring for supplying power supply voltage to a data circuit and clock circuit power supply wiring for supplying power supply voltage to a clock circuit are connected by a via and power supply wiring formed in a wiring layer that is different from (for example, that is located higher than the data circuit power supply wiring and the clock circuit power supply wiring) a wiring layer in which at least either the data circuit power supply wiring or the clock circuit power supply wiring is formed.

Description

CROSS-REFERENCE TO RELATED APPLICATION [0001] The disclosure of Japanese Patent Application No. 2005-137282 filed on May 10, 2005 including specification, drawings and claims is incorporated herein by reference in its entirety. BACKGROUND OF THE INVENTION [0002] 1. Field of the Invention [0003] The present invention relates to a semiconductor integrated circuit including a data circuit for performing signal processing of an input signal and a clock circuit for supplying a clock signal to the data circuit, and more particularly relates to technology for suppressing clock jitter that occurs in a semiconductor integrated circuit. [0004] 2. Description of the Related Art [0005] The circuits included in a semiconductor integrated circuit are classified into two groups: data circuits for performing processing of input signals and clock circuits for supplying clock signals to the data circuits. A clock signal input from a PLL circuit or a clock input terminal in a semiconductor integrated ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/10
CPCH01L27/118H01L27/0207
Inventor NAKAMURA, AKIHIRO
Owner PANASONIC CORP
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