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Mechanism for storing and extracting trace information using internal memory in microcontrollers

a microcontroller and internal memory technology, applied in the field of on-chip debug functionality in microcontrollers and microprocessors, can solve the problems of reducing the cost of implementation of trace features, reducing the cost of supporting, and reducing the availability of bus events for direct captur

Inactive Publication Date: 2006-12-07
ATMEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0012] A method and system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.

Problems solved by technology

With the advent of powerful microcontrollers with on-chip memories, the system bus resides within the device, and the bus events are no longer available for direct capture.
The problem becomes particularly noticeable as microcontrollers become ever more complex, with a corresponding increase in software complexity.
As many embedded systems involve real-time communication, control, or data processing, the debugging task becomes further complicated, as more debug features have to be non-intrusive, i.e., not disrupt the real-time software execution.
The trace features are nevertheless very bandwidth intensive.
The high bandwidth also strongly increases the cost of the debug tool 14, which requires complex and expensive hardware to capture and process the vast amount of high-speed trace information.

Method used

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  • Mechanism for storing and extracting trace information using internal memory in microcontrollers
  • Mechanism for storing and extracting trace information using internal memory in microcontrollers
  • Mechanism for storing and extracting trace information using internal memory in microcontrollers

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example

[0050] Assuming an implementation using 8-bit Nexus-compatible frames (2-bit MSEO control and 6-bit MDO data), and a big-endian 32-bit system bus, the RWD register 202 will be organized as shown in FIG. 4. Accordingly this register collects frames into bus-sized units.

[0051]FIG. 5 shows reconstructing a message from the trace buffer 206 (FIG. 3). In this example a message from the trace buffer 206 is shown after the CPU 32′ has been halted, with the RWA register 208 starting at 0x1000 and the CNT register=10 (i.e. the buffer size is 1024 words, or 4096 frames). When the trace was stopped, the WRAPPED status bit is set and the RWA register 208=0x 1234, so the last word of frame data written to the memory is located at 0x1230. The last two frames of the message still reside in the RWD register 202, which has been only partially filled.

[0052] If the RWD register 202 was not full by the time the breakpoint occurred, these frames are not written to the trace buffer 206. If the debug to...

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Abstract

It is the object of the present invention to provide a mechanism to store and retrieve trace information in on-chip system memory of microcontrollers. A microcontroller comprises a microprocessor and a memory device accessible through a data bus and an address bus coupled to the microprocessor. The microcontroller includes on-chip debug logic coupled to the microprocessor. The on-chip debug logic includes a low speed debug port and a mechanism for temporarily storing trace data on the memory, wherein the trace data can be retrieved via the low speed debug port by a debug tool. A method and system in accordance with the present invention will lower the cost of implementation of trace features in microcontrollers, and strongly reduce the cost of supporting such features in debug tools.

Description

FIELD OF THE INVENTION [0001] The present invention relates generally to on-chip debug functionality in microcontrollers and microprocessors that contain on-chip memory and more specifically to storing trace information in and extracting such information from on-chip memory. BACKGROUND OF THE INVENTION [0002]FIG. 1 shows a conventional debug system 10 with direct memory access and trace support. The debug system 10 comprises a host computer 12, a debug tool 14, a low speed debug interface 16, a high speed trace capture and processing unit 18, a low-speed debug port 15, a high-speed trace port 17, a microcontroller device 20 and a system memory 36. The microcontroller device 20 includes an on-chip debug logic 22, a frame buffer 24, an on-chip debug control 26, a bus monitor 28, a memory interface 30, a CPU 32 and a bus matrix 34. Traditionally, electronic systems with advanced control or data processing requirements would contain separate CPU 32 and memory devices, soldered onto the ...

Claims

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Application Information

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IPC IPC(8): G06F11/00
CPCG06F11/3636G06F9/22
Inventor PEDERSEN, FRODE MILCHARSETH, ARE
Owner ATMEL CORP