Memory Management Unit and Method for Memory Management

a memory management and memory technology, applied in the field of memory management units and methods for memory management, can solve the problems of time-consuming task switching, and achieve the effect of saving bus bandwidth and facilitating a fast hardware mechanism

a memory management and memory technology, applied in the field of memory management units and methods for memory management, can solve the problems of time-consuming task switching, and achieve the effect of saving bus bandwidth and facilitating a fast hardware mechanism

US20070277009A1Active Publication Date: 2007-11-29NXP USA INC
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  • Memory Management Unit and Method for Memory Management
  • Memory Management Unit and Method for Memory Management
  • Memory Management Unit and Method for Memory Management

Examples

Experimental program
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Embodiment Construction

[0013]FIG. 1 illustrates a memory management unit (MMU) 10 and its environment (collectively denoted 30), according to an embodiment of the invention. MMU 10 is conveniently a part of a system on chip that includes one or more processors, and conveniently is a part of a cellular phone, but this is not necessarily so.

[0014] The system on chip usually includes a peripheral bus that is connected to multiple peripherals devices such as I / O devices, audio and video devices, as well as memory modules.

[0015] The environment 30 includes a processor 18 that has two data buses XA 22 and XB 24 and an instruction bus P 26. Each of these data buses has data bits, address bits lines and control bits.

[0016] MMU 10 is connected to all three buses (XA, XB and P). The MMU 10 is further connected to the data channel 12 and to the instruction channel 14 and is further connected to processor 18 via line 28.

[0017] A data channel 12 is connected to buses XA 22 and XB 24. An instruction channel 14 that...

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Abstract

A memory management unit that includes: (i) multiple data segment descriptors, each data segment descriptor associated with a data memory segment; (ii) multiple program segment descriptors, each program segment descriptor associated with a program memory segment; and (iii) a controller, adapted to replace the content of the multiple data segment descriptors and the multiple program segment descriptors in response to a task switch. A method for memory management, the method includes: (i) providing multiple data segment descriptors; each data segment descriptor associated with a data memory segment, and providing multiple program segment descriptors, each program segment descriptor associated with a program memory segment; (ii) receiving and storing a program task identifier and a data task identifier; (iii) receiving a data access request and determining how to handle the data access request in response to a content of the multiple data segment descriptors; and (iv) receiving a program access request and determining how to handle the program access request in response to a content of the multiple program segment descriptors.

Description

FIELD OF THE INVENTION [0001] The present invention relates to a memory management unit and a method for memory management. BACKGROUND OF THE INVENTION [0002] Various configurations of memory management units are known in the art. Some configurations are illustrated in U.S. patent application 20020062427 of Chauvel et al., titled “Priority arbitration based on current task and MMU” and U.S. Pat. No. 5,835,962 of Chang, et al, titled “Parallel access micro-TLB to speed up address translation”, both being incorporated herein by reference. [0003] Modern processors access both cache memory modules and so caller higher level or external memory modules. The cache memory modules are usually accessed by virtual addresses while external memory modules are accessed by providing physical addresses. Typically, virtual addresses provided by a processor are translated to physical addresses by components other than the processor. U.S. patent application 20020082824 of Neiger al et., titled “virtua...

Claims

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Application Information

Patent Timeline
29 Nov 2007
Publication
US20070277009A1
IPC
G06F13/00; G06F12/1036
CPC
G06F12/1036; G06F12/1491; G06F12/1483
Inventors
ANSCHEL, MOSHE; BACHAR, MOSHE