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Generating scan test vectors for proprietary cores using pseudo pins

Inactive Publication Date: 2007-12-13
TEXAS INSTR INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

This approach enhances fault coverage in testing while maintaining protection of proprietary IP cores, simplifying test vector generation and reducing the complexity of additional test circuitry, thus preserving intellectual property.

Problems solved by technology

This poses several test challenges in core based / core dominated systems.

Method used

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  • Generating scan test vectors for proprietary cores using pseudo pins
  • Generating scan test vectors for proprietary cores using pseudo pins
  • Generating scan test vectors for proprietary cores using pseudo pins

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Embodiment Construction

[0033] The method proposed by the present invention addresses the problem of testing integrated Intellectual Property (IP) cores through the proper use of insertion of test circuitry and automatic test pattern generation (ATPG) tools, when used in the context of core based, or core dominated, digital circuit designs. This leads to significant fault coverage improvements, while at the same time, maintaining protection of the proprietary IP core. One technique by which this may be achieved is as follows.

[0034] An internal scan chain only, partial netlist version of the embedded core in question is first extracted or developed, including only the key input and output logic cones associated with the scan flip-flops which are fed from primary inputs, and including the scan flip-flops which are driving primary output ports or pins of the core extracted. This applies as well to cores without any direct boundary scan implementations. This task may be wholly or partially performed using kno...

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Abstract

A method generates test vectors for a customer designed integrated circuit having an embedded vendor circuit. The embedded vendor circuit has a proprietary circuit and a nonproprietary circuit. At least one pseudo input is defined to represent a portion of the nonproprietary circuit to emulate the nonproprietary circuit output. An output node of the embedded vendor circuit to which an input of the customer designed circuit is connectable is identified. A test netlist is created which represents circuitry that produces output states at the output node which would be generated by the embedded vendor circuit thereat. The test netlist includes at least one pseudo input and the output node, without including a full netlist of either the proprietary or nonproprietary circuits, and can be used to generate scan test vectors for the customer designed integrated circuit by the automatic test vector generating software program.

Description

[0001] This application is a divisional of prior application Ser. No. 10 / 771,775, filed Feb. 2, 2004, currently pending; [0002] Which is a divisional of prior application Ser. No. 09 / 681,598, filed May 4, 2001, now U.S. Pat. No. 6,697,982, issued Feb. 24, 2004.COPYRIGHT STATEMENT [0003] A portion of the disclosure of this patent document contains material which is subject to copyright or mask work protection. The copyright or mask work owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright or mask work rights whatsoever BACKGROUND OF INVENTION [0004] 1. Field of Invention [0005] This invention relates to improvements in testing integrated circuits, in general, and to improvements in methods for testing embedded core integrated circuits while preserving the intellectual property contained in the core circuits, that is, ...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F11/00G01R31/3183G01R31/3185
CPCG01R31/318307G01R31/318378G06F11/267G01R31/318572G01R31/318547
Inventor CHAKRAVARTHY, SRINIVASAPAREKHJI, RUBIN A.HERNANDEZ, JULIO C.BUTLER, KENNETH M.
Owner TEXAS INSTR INC