Storage nodes, phase change memories including a doped phase change layer, and methods of operating and fabricating the same

Abstract

Example embodiments may provide a doped phase change layer and a method of operating and fabricating a phase change memory with the example embodiment doped phase change layer. The phase change memory may include a storage node having a phase change layer and a switching device, wherein the phase change layer includes indium with a concentration ranging from about 5 at % to about 15 at %. The phase change layer may be a GST layer that includes indium. The phase change layer may be a GST layer that includes gallium.

Description

PRIORITY STATEMENT [0001] This application claims the benefit of Korean Patent Application No. 10-2006-0062409, filed on Jul. 4, 2006, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. BACKGROUND [0002] 1. Field [0003] Example embodiments may relate to a doped phase change layer, for example, to a phase change memory device having a doped phase change layer and a method of operation of the phase change memory device. [0004] 2. Description of the Related Art [0005] Phase change random access memory (PRAM), flash memory, ferroelectric random access memory (FeRAM), and / or magnetic random access memory (MRAM) may be a non-volatile memory devices. The structural difference between the PRAMs and other non-volatile memories may be a storage node. [0006] A storage node of the PRAM may include a phase change layer. The phase of the phase change layer may change to an amorphous state from a crystalline state at a critical ...

AI Technical Summary

Benefits of technology

[0014] Example embodiments may provide a phase change memory having a doped phase change layer that may have a lowered reset current, a lowered melting point, and / or an increased resistance.

Problems solved by technology

Because the drive current of a transistor may be determined by its size, it may be difficult to reduce the size of the transistor without reducing the reset current.

Increase in PRAM integration may be difficult without reducing the reset current.

Images