Ceramic Package in Which Far End Noise is Reduced Using Capacitive Cancellation by Offset Wiring

Abstract

A mechanism for reducing the vertical cross-talk interference experienced in signal lines due to the inductive affects from signal lines in other signal planes of a multi-layer ceramic package is provided. With the apparatus and method, one or more vias in the multi-layer ceramic package may be removed from the structure to provide area through which an offset of the signal lines may pass. Because these offsets of the signal lines exist in parallel planes above or below each other, with no ground lines existing directly between these signal line offsets, a capacitive cross-talk is introduced into the signal lines. This capacitive cross-talk is opposite in polarity to the inductive cross-talk already experienced by the signal lines. As a result, the capacitive cross-talk tends to negate or reduce the inductive cross-talk thereby reducing the far end noise in the signal line.

Description

BACKGROUND OF THE INVENTION [0001] 1. Technical Field [0002] The present invention relates generally to an improved apparatus and method for noise reduction in multi-layered packages. More specifically, the present invention is directed to an apparatus and method for far end noise reduction in multi-layered ceramic packages using capacitive cancellation by offset wiring. [0003] 2. Description of Related Art [0004] As Very Large Semiconductor Integrated (VLSI) circuits become more dense, there is a need in the art to have semiconductor packaging structures that can take full advantage of the density and speed provided by state of the art VLSI devices. Present day modules made of ceramic, typically multilayered ceramic modules, are normally mounted onto cards or boards, with cards or boards combined together to form the central processing unit (CPU) of a computer. The multilayer ceramic (MLC) modules typically have VLSI chips mounted on the top surface. [0005] Multilayer modules are u...

AI Technical Summary

Benefits of technology

This approach significantly reduces far end noise, achieving a 0-37.2% reduction in noise levels, thereby enhancing signal integrity and increasing maximum signaling rates and performance without increasing package costs or wire channel penalties.

Problems solved by technology

Such inductance effects may arise from switching, for example, and are particularly problematic in power and ground leads.

Inductance effects in the package can cause ground bounce, signal cross-talk and the like.

Increasing circuit size and speed also impact the heat dissipation ability of the package.

VLSI and Ultra Large Semiconductor Integrated (ULSI) chips are especially designed for high performance applications and are thus limited by noise.

The noise is caused by a high number of simultaneously switching off-chip drivers (OCD noise) and by a high number of simultaneously switching latches and the associated logic gates (logic noise).

Both noise sources impact and restrict the on-chip and off-chip performance and jeopardize the signal integrity.

Both noise sources generate noise due to line-to-line coupling and due to the collapse of the voltage-ground (GND) system.

This interaction, i.e. cross-talk, between high speed signals introduces inter-symbol interference (ISI) on the nets that severely limits the maximum signaling rates and performance on these nets.

At a certain threshold, inter-symbol interference will compromise the integrity of the received data.

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