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Semiconductor device

a semiconductor and device technology, applied in the direction of semiconductor devices, electrical equipment, transistors, etc., can solve the problems of control circuit malfunction, semiconductor devices increasingly tend to easily malfunction in the future, and the control circuit may malfunction

Inactive Publication Date: 2008-06-05
KK TOSHIBA
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0007]In an aspect the present invention provides a semiconductor device, comprising: a semiconductor substrate of a first conductivity type; a well layer of the first conductivity type selectively formed on the semiconductor substrate; a first diffused layer of a second conductivity type selectively formed on the well layer; a second diffused layer of the second conductivity type formed on the well layer apart from the first diffused layer; a control electrode formed on an insulating film between the first diffused layer and the second diffused layer; a main electrode formed on each of the first diffused layer and the second diffused layer; a first trench formed in the semiconductor substrate surrounding the well layer, and a third diffused layer of the second conductivity type formed contacting to the first trench, wherein the second diffused layer and the third diffused layer are electrically kept at the same potential.
[0008]In another aspect the present invention provides a semiconductor d

Problems solved by technology

If such the semiconductor device containing the power transistor therein drives an inductive load such as a coil and a motor, the control circuit may malfunction under the influence of a parasitic transistor.
In a word, the semiconductor device increasingly tends to easily malfunction in the future under the influence of the parasitic transistor at the same level.

Method used

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first embodiment

[0043]FIG. 1 is a cross-sectional view of the major part of a first embodiment of the present invention. In a semiconductor device according to the first embodiment of the present invention, the control unit 110 and the low-side MOSFET 127 in the synchronous buck DC-DC converter as shown in FIG. 11 are configured in section as shown in FIG. 1.

[0044]The semiconductor device according to the first embodiment comprises a P-type semiconductor substrate 1, and a P-type well layer 2 and an N-type well layer 3 in the surface of the P-type semiconductor substrate 1 as shown in FIG. 1. The region including the P-type well layer 2 formed therein serves as the low-side MOSFET 127 in the power unit 120 (FIG. 11). The region including the N-type well layer 3 formed therein serves as the control unit 110 (FIG. 11). A first trench 4 is formed surrounding the P-type well layer 2, that is, trenching the P-type semiconductor substrate 1 in depth between the P-type well layer 2 and the N-type well lay...

second embodiment

[0053]A semiconductor device according to a second embodiment of the present invention is described next. FIG. 3 is a cross-sectional view of the major part of the second embodiment of the present invention. In the semiconductor device according to the second embodiment of the present invention, the control unit 110 and the low-side MOSFET 127 in the synchronous buck DC-DC converter as shown in FIG. 11 are configured in section as shown in FIG. 3. A plane pattern of the second embodiment is similar to FIG. 2 of the first embodiment.

[0054]The semiconductor device according to the second embodiment comprises a second trench 4′ formed therein, in addition to the first trench 4, different from the first embodiment. The same parts as those in the first embodiment are denoted with the same reference numerals and omitted from the following description.

[0055]The second trench 4′ is formed surrounding the first trench 4, that is, between the first trench 4 and the N-type well layer 3. An N+-...

third embodiment

[0057]A semiconductor device according to a third embodiment of the present invention is described next. FIG. 4 is a cross-sectional view of the major part of the third embodiment of the present invention. In the semiconductor device according to the third embodiment of the present invention, the control unit 110 and the low-side MOSFET 127 in the synchronous buck DC-DC converter as shown in FIG. 11 are configured in section as shown in FIG. 4. A plane pattern of the third embodiment is similar to FIG. 2 of the first embodiment.

[0058]The semiconductor device according to the third embodiment comprises an N-type guard ring layer 31 formed therein, in addition to the first trench 4, different from the first embodiment. The same parts as those in the first embodiment are denoted with the same reference numerals and omitted from the following description.

[0059]The N-type guard ring layer 31 is formed surrounding the first trench 4, that is, between the first trench 4 and the N-type well...

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PUM

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Abstract

A semiconductor device comprises a semiconductor substrate of the first conductivity type. A well layer of the first conductivity type is selectively formed on the semiconductor substrate. A first diffused layer of the second conductivity type is selectively formed on the well layer. A second diffused layer of the second conductivity type is formed on the well layer apart from the first diffused layer. A control electrode is formed on an insulating film between the first diffused layer and the second diffused layer. A main electrode is formed on each of the first diffused layer and the second diffused layer. A first trench is formed in the semiconductor substrate surrounding the well layer. A third diffused layer of the second conductivity type is formed contacting to the first trench. The second diffused layer and the third diffused layer are electrically kept at the same potential.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2006-323136, filed on Nov. 30, 2006, the entire contents of which are incorporated herein by reference.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an inductive load driving circuit.[0004]2. Description of the Related Art[0005]In recent years, downsizing of electronics and reducing power consumption therein requires downsized semiconductor devices mounted thereon with reduced power consumption and increased operation speeds. For example, a semiconductor device for power supplies and motor drivers has been downsized by containing a power transistor therein and packaging it in a small package. Alternatively, the absolute value of each bias current in analog circuits for controlling the power transis...

Claims

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Application Information

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IPC IPC(8): H01L27/088
CPCH01L21/763H01L27/088H01L21/823481
Inventor NAKAMURA, KAZUTOSHI
Owner KK TOSHIBA