Chip package structure and method for fabricating the same

Abstract

The invention provides a chip package structure and method for fabricating the same. The chip package structure includes a carrier substrate. A plurality of isolated conductive layers is disposed on the carrier substrate. At least one chip is disposed on the carrier substrate, wherein the chip has a plurality of electrodes. The electrodes are electrically connected to the conductive layers. A conductive path is disposed in the carrier substrate, electrically connected to the electrodes through the conductive layers, wherein the conductive path comprises a plurality of laminating holes.

Description

FIELD OF THE INVENTION [0001]The present invention relates to a chip package structure and method for forming the same, and in particular relates to a light emitted chip package structure and method for forming the same.DESCRIPTION OF THE RELATED ART [0002]The chip packaging process is one of the important processes for forming chips. A chip package structure, not only provides an interface for connecting chips to electronic elements, but also provides protection for chips from environmental contaminants, along with other functions.[0003]With increasing development of the semiconductor fabrication process, chips are being formed in smaller and smaller dimensions. However, due to the ever-decreasing size and the ever-increasing density of the chips, number and density of the input / output (I / O) connections of chips have increased. Therefore, the chip area for conductive paths between chips and outside features formation is not enough. The fabrication cost can not be reduced due to a...

AI Technical Summary

Benefits of technology

[0025]The exemplary embodiments of the chip package structure 500 have the following advantages. For example, the chip package structure is fabricated by a wafer level package process to package the chip array. Therefore, the chip package structure has much smaller dimensions than that of the conventional wire-bonding type chip package structure. When the chip package structure is arranged in a pixel array for illumination or display, an exemplary embodiment of the chip package structure may allow the pixel array to have a smaller pitch between each light emitting device. Therefore, improving pixel continuity and visual effect. Additionally, the conductive path is constructed by laminated the upper and lower holes, wherein the upper and lower holes further comprise a lateral conductive layer therebetween to increase conductive area of the hole conducting layers.

Problems solved by technology

Therefore, the chip area for conductive paths between chips and outside features formation is not enough.

The fabrication cost can not be reduced due to a huge amount of the golden wires using as I / O connections between chip arrays and outside features, especially in package structure composed by optoelectronic chips.

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