Semiconductor package structure and fabricating method of semiconductor package structure

Abstract

A semiconductor package structure includes a dielectric layer, a patterned metal layer, a carrier, a metal layer and a semiconductor die. The dielectric layer has a first surface, a second surface and an opening. The patterned metal layer is disposed on the first surface. The carrier is disposed at the second surface and has a third surface, a fourth surface and at least a through hole. A portion of the third surface and the through hole are exposed by the opening. The metal layer is disposed on the fourth surface and has a containing cavity and at least a heat conductive post extending from the fourth surface and disposed in the through hole. An end of the heat conductive post protrudes away from the third surface, and the containing cavity is located on the end of the heat conductive post. The semiconductor die is located in the containing cavity.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application claims the priority benefit of Taiwan application serial no. 99122521, filed on Jul. 8, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The invention generally relates to a package structure and a fabricating method thereof, and more particularly, to a package and the carrier structure thereof and a fabricating method thereof with demand on high heat conduction performing.[0004]2. Description of Related Art[0005]The purpose of chip package is to provide a chip with an appropriate signal path, a heat conduction path and structure protection. The traditional wire bonding technique usually adopts a leadframe as a carrier of the chip. Along with gradually increasing the bonding point density of a chip, the leadframe is unable to provide a higher bonding point density, so that ...

AI Technical Summary

Benefits of technology

[0007]Accordingly, the invention is directed to a semiconductor package structure having better heat dissipation efficiency and low CTE property.

Problems solved by technology

Along with gradually increasing the bonding point density of a chip, the leadframe is unable to provide a higher bonding point density, so that it is replaced by a package substrate with high bonding point density, where the chip is packed onto the package substrate through conductive media such as metal wires or bumps.

When paste, for example a silver epoxy, is used as the material of the adhesive layer, due to the poor thermal conducting rate (less than 20 W / mK), high coefficient of thermal expansion (CTE) (greater than 30 ppm / K) and poor adhering strength of the silver epoxy, so that when the heat produced by the chip is transferred to the package substrate through the adhesive layer, an increasing thermal resistance is caused by the adhesive layer, which further leads to poor heat conduction and decrease the strength of the adhesive layer and even destroy the adhesive layer when thermal stress occurs.

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