Semiconductor package structure and fabricating method of semiconductor package structure
a semiconductor and package technology, applied in the field of package structure, can solve the problems of reducing the strength of the adhesive layer, poor heat conduction, and providing a higher bonding, and achieve the effect of low cte property and improved heat dissipation efficiency
Patent Information
- Authority / Receiving Office
- US · United States
- Patent Type
- Applications(United States)
- Current Assignee / Owner
- Publication Date
- 2012-01-12
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Abstract
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of Taiwan application serial no. 99122521, filed on Jul. 8, 2010. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of specification.BACKGROUND OF THE INVENTION
[0002] 1. Field of the Invention
[0003] The invention generally relates to a package structure and a fabricating method thereof, and more particularly, to a package and the carrier structure thereof and a fabricating method thereof with demand on high heat conduction performing.
[0004] 2. Description of Related Art
[0005] The purpose of chip package is to provide a chip with an appropriate signal path, a heat conduction path and structure protection. The traditional wire bonding technique usually adopts a leadframe as a carrier of the chip. Along with gradually increasing the bonding point density of a chip, the leadframe is unable to provide a higher bonding point density, so that ...
Examples
Embodiment Construction
[0036]FIG. 1 is a cross-sectional diagram of a semiconductor package structure according to an embodiment of the invention. Referring to FIG. 1, in the embodiment, a semiconductor package structure 100a includes a dielectric layer 110, a patterned metal layer 120, a carrier 130, a metal layer 140 and a semiconductor die 150.
[0037]In more details, the dielectric layer 110 has a first surface 112 and a second surface 114 opposite to the first surface 112 and an opening 116, in which the opening 116 goes through the first surface 112 and the second surface 114. The patterned metal layer 120 is disposed on the first surface 112 of the dielectric layer 110, in which the patterned metal layer 120 exposes the first surface 112 of a portion of the metal layer 110. In the embodiment, the patterned metal layer 120 can serve as the bonding pad for a successive wire bonding process. The carrier 130 is disposed at the second surface 114 of the dielectric layer 110 and has a third surface 132 and...