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Method for fabricating semiconductor devices using stress engineering

a technology of stress engineering and semiconductor devices, applied in the direction of semiconductor devices, basic electric elements, electrical equipment, etc., can solve the problems of high current during operation and correspondingly faster device operation

Inactive Publication Date: 2012-03-22
TAIWAN SEMICON MFG CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Specifically, an increase in the mobility of carriers in the transistor channel leads to a higher current during operation and correspondingly faster device operation.

Method used

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  • Method for fabricating semiconductor devices using stress engineering
  • Method for fabricating semiconductor devices using stress engineering
  • Method for fabricating semiconductor devices using stress engineering

Examples

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Embodiment Construction

[0012]The following embodiments are described in sufficient detail to enable those skilled in the art to make and use the invention. It is to be appreciated that other embodiments would be evident based on the present disclosure, and that system, process, or mechanical changes may be made without departing from the scope of the present invention.

[0013]FIGS. 1 to 5 are cross-sectional views illustrating process steps for fabricating Metal Oxide Field Effect Transistors (MOSFET) in accordance with one embodiment of the invention. It should be noted, however, that embodiments of the invention are described in the context of fabricating MOSFETs for illustrative purposes only and that the invention may also be applicable to the fabrication of other semiconductor devices such as but not limited to multi-gate transistors, annular gate transistors and high voltage transistors.

[0014]Additionally, it is to be understood that a plurality of conventional processes that are well known in the art...

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Abstract

There is provided a method for fabricating a semiconductor device comprising the formation of a first device in the first device region, the first device comprising first diffusion regions. A stressor layer covering the substrate in the first device region and the first device is subsequently formed, the stressor layer having a first stress value. A laser anneal to memorize at least a portion of the first stress value in the first device is carried out followed by an activation anneal after the laser anneal to activate dopants in the first diffusion regions.

Description

CROSS-REFERENCE TO RELATED APPLICATION[0001]This application is a continuation-in-part of U.S. application Ser. No. 12 / 510,276 filed Jul. 28, 2009, which is a continuation of U.S. application Ser. No. 11 / 940,326 filed Nov. 15, 2007, now issued as U.S. Pat. No. 7,592,270 which is a continuation of U.S. application Ser. No. 11 / 304,412 filed Dec. 15, 2005, which is now abandoned. These applications are hereby incorporated by reference in their entireties.TECHNICAL FIELD[0002]The present invention relates to generally to methods for fabricating semiconductor devices, and more particularly to methods for improving carrier mobility in semiconductor devices using stress engineering.BACKGROUND ART[0003]Integrated circuits (ICs) comprising many tens of thousands of semiconductor devices including field effect transistors (FETs) are a cornerstone of modern microelectronic systems. A common active device within an integrated circuit is the metal-oxide-semiconductor field effect transistor (MOS...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L21/225
CPCH01L21/823807H01L29/7843H01L21/823864
Inventor YEONG, SAI HOOIWANG, TAOPANDEY, SHESH MANIYEO, CHIA CHINGLEUNG, YING KEUNGQUEK, ELGIN KIOK BOONE
Owner TAIWAN SEMICON MFG CO LTD
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