Instruction execution based on outstanding load operations

a technology of execution and load operations, applied in the field of program execution, can solve problems such as complicated thread schedulers

Inactive Publication Date: 2012-03-29
NVIDIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0009]The outstanding load count enables a scheduler to track the number of outstanding ...

Problems solved by technology

Extreme multi-threading requi...

Method used

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  • Instruction execution based on outstanding load operations
  • Instruction execution based on outstanding load operations
  • Instruction execution based on outstanding load operations

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Embodiment Construction

[0021]In the following description, numerous specific details are set forth to provide a more thorough understanding of the present invention. However, it will be apparent to one of skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

System Overview

[0022]FIG. 1 is a block diagram illustrating a computer system 100 configured to implement one or more aspects of the present invention. Computer system 100 includes a central processing unit (CPU) 102 and a system memory 104 communicating via an interconnection path that may include a memory bridge 105. Memory bridge 105, which may be, e.g., a Northbridge chip, is connected via a bus or other communication path 106 (e.g., a HyperTransport link) to an I / O (input / output) bridge 107. I / O bridge 107, which may be, e.g., a Southbridge chip, receives user input from one or mor...

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Abstract

One embodiment of the present invention sets forth a technique for scheduling thread execution in a multi-threaded processing environment. A two-level scheduler maintains a small set of active threads called strands to hide function unit pipeline latency and local memory access latency. The strands are a sub-set of a larger set of pending threads that is also maintained by the two-leveler scheduler. Pending threads are promoted to strands and strands are demoted to pending threads based on latency characteristics, such as whether outstanding load operations have been executed. The longer latency of the pending threads is hidden by selecting strands for execution. When the latency for a pending thread is expired, the pending thread may be promoted to a strand and begin (or resume) execution. When a strand encounters a latency event, the strand may be demoted to a pending thread while the latency is incurred.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation of U.S. patent application titled, “Two-Level Scheduler for Multi-Threaded Processing”, filed on Jun. 1, 2011 and having Ser. No. 13 / 151,094 (Attorney Docket Number NVDA / SC-10-0208-US0-US1) which claims priority benefit to U.S. provisional patent application titled, “Strands: Exploiting Sub-Threads Free from Long-Latency Operations”, filed on Sep. 24, 2010 and having Ser. No. 61 / 386,248 (Attorney Docket Number NVDA / SC-10-0208-US0). This application also claims priority benefit to U.S. patent application titled, “Multi-Stranding,” filed on Sep. 24, 2010 and having Ser. No. 61 / 386,244 (Attorney Docket Number NVDA / SC-10-0209-US0). These related applications are also hereby incorporated by reference in their entirety.BACKGROUND OF THE INVENTION[0002]1. Field of the Invention[0003]The present invention generally relates to program execution and more specifically to instruction execution based on outstanding l...

Claims

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Application Information

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IPC IPC(8): G06F9/30G06F9/312
CPCG06F9/3851G06F9/3887G06F9/4881
Inventor DALLY, WILLIAM JAMESLINDHOLM, JOHN ERIK
Owner NVIDIA CORP
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