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3 results about "Two-level scheduling" patented technology

Two-level scheduling is a computer science term to describe a method to more efficiently perform process scheduling that involves swapped out processes. Consider this problem: A system contains 50 running processes all with equal priority. However, the system's memory can only hold 10 processes in memory simultaneously. Therefore, there will always be 40 processes swapped out written on virtual memory on the hard disk. The time taken to swap out and swap in a process is 50 ms respectively.

GPU chip temperature sensing thread bundle management method

PendingCN121960595AHigh precisionReduce hot spot temperatureBiological modelsThermometer applicationsParallel computingThermal aware
The invention discloses a GPU (Graphic Processing Unit) chip temperature sensing thread bundle management method, relates to the technical field of GPU chip application, and solves the problems of low efficiency of a thermal management strategy and the like caused by the fact that a thermal prediction method in the prior art cannot cover hot spots of a whole chip, is high in modeling complexity and poor in real-time performance. The thermal prediction model is used for predicting the hot spot temperature of the chip in the running process of the graphics processor; the TAWS scheduling module is constructed based on a two-stage Warp scheduling strategy and is used for comparing the hot spot temperature with a preset maximum temperature threshold value and selectively executing a normal scheduling mode or a temperature control scheduling mode; the temperature of the chip is regulated and controlled; and when the duration of the high-temperature state exceeds the preset maximum allowable duration, the TAWS scheduling module triggers a scheduling freezing mechanism to realize safety control of the chip temperature. According to the method, cross-architecture high-precision generalization, a low-overhead instruction-level thermal sensing scheduling mechanism, refined analysis of instruction-level thermal characteristics and the like are realized.
Owner:JILIN UNIVERSITY

An unmanned aerial vehicle cluster simulation scheduling method for time-sensitive target tasks

The application relates to a UAV cluster simulation scheduling method for time-sensitive target tasks, belonging to the field of UAV clusters. The method comprises the following steps: receiving a cluster situation input frame and writing the frame into a time-sensitive cache area; the time-sensitive cache area extracts the latest input frame in a scheduling cycle, and updates a data center according to the latest input frame; a group-cluster two-level scheduling architecture is adopted, the UAV state information of the data center is called, the task area is divided into a plurality of sub-task areas, the UAV cluster is clustered according to the sub-task areas and reaches the sub-task areas in a formation, the UAVs in each cluster cooperatively search in different sub-task areas, when any UAV discovers a time-sensitive target, the remaining UAVs in the cluster are immediately assembled and a surrounding task for the time-sensitive target is issued; the UAV cluster completes the surrounding task according to scheduling output information and the time-sensitive target, and waits for the next task execution. The application solves the problem that the prior art cannot realize a low-lag, sustainable and scalable hierarchical scheduling closed loop.
Owner:SUN YAT SEN UNIV

A spaceborne deterministic partition scheduling method supporting a multi-core processor

The application discloses a kind of support multi-core processor's spaceborne deterministic partition scheduling method, through partition division, two-level scheduling, multiple complex disordered tasks of spaceborne computer are arranged into determined execution sequence, according to time window planning partition, the execution time of each partition is determined, support user according to priority configuration task's processor core, for high time sequence and real-time requirement task, can be bound to specified processor core and run, for time sequence and real-time requirement not high task, can be allocated idle processor core by system and run, on the one hand, can ensure the time sequence determinacy and determinacy of execution time of task, solve the problem of uncertain scheduling sequence caused by multi-core competition execution multitask, on the other hand, can reduce the idle rate of processor core, improve the scheduling efficiency of multi-core. While having partition exception state detection and dynamic management function, improve the reliability and expansibility of system.
Owner:BEIJING INST OF SPACECRAFT SYST ENG