Bump for semiconductor package, semiconductor package having bump, and stacked semiconductor package

Abstract

A bump for a semiconductor package includes: a first bump formed on a semiconductor chip and having at least two land parts and a connection part which connects the land parts and has a line width smaller than the land parts; and a second bump formed on the first bump and projecting on the land parts of the first bump in shapes of a hemisphere.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS[0001]The present application claims priority to Korean patent application number 10-2010-101734 filed on Oct. 19, 2010, which is incorporated herein by reference in its entirety.TECHNICAL FIELD[0002]The present invention generally relates to a bump for a semiconductor package, and more particularly a semiconductor package having the bump, and a stacked semiconductor package.BACKGROUND OF THE INVENTION[0003]As various electric / electronic products are scaled down, research has been actively conducted to mount an increased number of chips to a substrate within a limited size and thereby realize miniaturization and high capacity. Accordingly, the size and thickness of a semiconductor package gradually decrease. For example, a chip size package, in which a chip size is no less than 80% of the total size of a semiconductor package, has been suggested. The chip size package has been developed into various types due to advantages resulting from a ligh...

AI Technical Summary

Benefits of technology

[0007]Embodiments of the present invention are directed to a bump for a semiconductor package, which can improve the manufacturing yield, reduce the manufacturing cost and decrease the number of processes, a semiconductor package having the bump, and a stacked semiconductor package.

Problems solved by technology

While soldering using a lead frame may enhance performance in terms of a process and reliability, issues may be caused in terms of electrical characteristics due to the fact that a transfer length of an electrical signal is long.

In the flip chip package, since transfer of an electrical signal between the semiconductor chip and the printed circuit board is implemented only by the bumps, a signal transfer length becomes very short.

However, if even one of the bumps connecting the semiconductor chip and the printed circuit board is poorly connected, a corresponding product cannot be used, which causes a decrease in manufacturing yield.

While this method may lead to better manufacturing yield, since the redistribution lines and the bumps should be individually formed using separate masks, the manufacturing costs and the number of processes increase due to separate formation of the masks.

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