Apparatus and methods for testing memory cells

Abstract

Apparatus and methods are provided for concurrently selecting multiple arrays of memory cells when accessing a memory element. A memory element includes a first array of one or more memory cells coupled to a first bit line node, a second array of one or more memory cells coupled to a second bit line node, access circuitry for accessing a first memory cell in the first array, a first transistor coupled between the first bit line node and the access circuitry, and a second transistor coupled between the second bit line node and the access circuitry. A controller is coupled to the first transistor and the second transistor, and the controller is configured to concurrently activate the first transistor and the second transistor to access the first memory cell in the first array.

Description

TECHNICAL FIELD[0001]Embodiments of the subject matter described herein relate generally to electronic circuits, and more particularly, relate to memory elements for use in computing devices and methods for testing the same.BACKGROUND[0002]Memory elements are widely used in computing applications. For example, a typical computing device may include a combination of volatile and non-volatile memory elements to maintain data, program instructions, and the like that are accessed by a processing unit (e.g., a CPU) during operation of the computing device. Latencies associated with memory accesses impair performance of the computing device. Accordingly, a processing unit typically includes one or more memory elements, known as caches, to provide requested data or instructions to the processing unit with reduced latency. Typically, caches are realized as volatile memory elements. For example, an array of static random access memory (SRAM) cells may be used to provide a cache on a common d...

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