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Efficient buffering for a system having non-volatile memory

a non-volatile memory and buffering technology, applied in memory architecture accessing/allocation, instruments, sustainable buildings, etc., can solve the problem of net performance burden of buffering, and achieve the effect of reducing read energy and buffering overhead, efficient buffering, and increasing system performan

Inactive Publication Date: 2012-08-30
APPLE INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0004]Systems and methods are disclosed for efficient buffering of a system having non-volatile memory (“NVM”). The system can select to buffer writes where the buffering will increase system performance, and select to program writes directly to a NVM where the buffering would be a net performance burden. In some embodiments, a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the system can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the system can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the system can dispatch the commands in a single transaction.

Problems solved by technology

The system can select to buffer writes where the buffering will increase system performance, and select to program writes directly to a NVM where the buffering would be a net performance burden.

Method used

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  • Efficient buffering for a system having non-volatile memory
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  • Efficient buffering for a system having non-volatile memory

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Embodiment Construction

[0013]Systems and methods for efficient buffering of a system having non-volatile memory (“NVM”) are provided. A control circuitry of a system can use heuristics to determine whether or not to buffer write commands received from a file system. Any suitable heuristics can be used, such as, for example, the size of a write command, the number of dispatched write command immediately preceding the write command, the number of remaining write commands saved in a queue, the amount of available space in memory, the size of a buffer, and input / output (“I / O”) patterns.

[0014]In some embodiments, the control circuitry can determine whether or not to buffer a write command based on the size of command. For example, if the control circuitry determines that the write command is a relatively small command (e.g., the size of the write command is below a pre-determined threshold), the control circuitry can select a buffered path for the write command (e.g., transfer the write command to a buffer in ...

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PUM

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Abstract

Systems and methods are disclosed for efficient buffering for a system having non-volatile memory (“NVM”). In some embodiments, a control circuitry of a system can use heuristics to determine whether to perform buffering of one or more write commands received from a file system. In other embodiments, the control circuitry can minimize read energy and buffering overhead by efficiently re-ordering write commands in a queue along page-aligned boundaries of a buffer. In further embodiments, the control circuitry can optimally combine write commands from a buffer with write commands from a queue. After combining the commands, the control circuitry can dispatch the commands in a single transaction.

Description

BACKGROUND OF THE DISCLOSURE[0001]NAND flash memory, as well as other types of non-volatile memories (“NVMs”), are commonly used for mass storage. For example, consumer electronics such as portable media players often include flash memory to store music, videos, and other media.[0002]Because a file system of a device may perform multiple small synchronous input / outputs (“I / Os”), die parallelism cannot be achieved in some cases. This consequently may reduce system bandwidth, and increase the latency for programming the pages of a NVM.[0003]In some scenarios, the latency for programming a NVM can be improved by buffering one or more I / Os prior to programming the I / Os to the NVM. However, in other scenarios, if I / Os can instead be directly programmed to the NVM, indiscriminate buffering of all I / Os received from a file system may actually slow down the programming process.SUMMARY OF THE DISCLOSURE[0004]Systems and methods are disclosed for efficient buffering of a system having non-vol...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F12/00
CPCG06F13/1673G06F21/71G06F21/79G06F2221/2107G06F3/0656G06F3/068Y02B60/1228G06F3/061Y02D10/00G06F12/00G06F13/14G11C16/02G06F3/0613G06F3/0659G06F3/0679G06F12/0246G06F12/1408G06F2212/1052
Inventor POST, DANIEL J.WAKRAT, NIR
Owner APPLE INC
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