Integrated circuit chip and semiconductor memory device
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first embodiment
[0026]FIG. 2 illustrates a semiconductor memory device in accordance with the present invention. FIG. 2 illustrates that one data pad DQ PAD is provided. However, the present invention may be also applied a semiconductor memory device including a plurality of data pads DQ PAD. Hereafter, one data pad DQ PAD is provided as an example, for illustration purposes.
[0027]The semiconductor memory device includes a cell array area 400, a plurality of data buses GIO0:N>, a parallel-serial conversion circuit 500, an inversion determination unit 600, and a data output circuit 700.
[0028]The cell array area 400 includes a plurality of cells, and each cell stores data.
[0029]The plurality of data buses GIO0:N> are configured to transmit a data outputted from the cell array area 400 to the parallel-serial conversion circuit 500. In this embodiment, data may be successively loaded into the plurality of data buses GIO0:N>. When data is successively loaded into the plurality of data buses GIO0:N>, the...
second embodiment
[0039]FIG. 4 illustrates a semiconductor memory device in accordance with the present invention. The semiconductor memory device of FIG. 4 is an example of a semiconductor memory device that may be applied where state information of the semiconductor memory device indicates whether data is normally stored in a cell array area 400 or not. To test whether data is normally stored in the cell array area 400 or not, test data is stored in the cell array area 400, and the stored data is read from the cell array area 400 and compared. When all of the stored data is identical, the cell array area 400 is determined to be normal, and when any one of the stored data is different, some cells of the cell array area 400 are determined to be defective. For this operation, the inversion determination unit 600 may include a data comparison section 610, a first delay section 620, a second delay section 630, and a latch section 640.
[0040]The data comparison section 610 is configured to receive data fr...
third embodiment
[0048]FIG. 6 illustrates a semiconductor memory device in accordance with the present invention. The semiconductor memory devices illustrated in FIGS. 2 and 4 converts parallel data PDATA0:N> into serial data and subsequently inverts the serial data PRE_DATA in response to the inversion signal INV_EN. However, the semiconductor memory device illustrated in FIG. 6 inverts parallel data PDATA0:N> in response to the inversion signal INV_EN and subsequently converts the inverted data into serial data.
[0049]Specifically, the semiconductor memory device in accordance with the third embodiment of the present invention includes a cell array area 400, a plurality of data buses GIO0:N>, a pipe latch 510, an inversion determination unit 600, and a parallel data inversion unit 800. The configurations and operations of the cell array area 400, the data buses GIO0:N>, the pipe latch 510, and the inversion determination unit 600 are the same as the configurations and operations described with refe...
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