Amplification circuit adjusting duty cycle of output signal and receiver including the same

Abstract

A receiver includes a first stage buffer, a second stage buffer and a third stage buffer. The first stage buffer includes an input portion electrically coupled to a first voltage node, and configured to change a voltage level of an output node in response to an input signal, first and second load portions electrically coupled between a second voltage node and the output node, and electrically coupled to each other and a duty cycle adjustment portion electrically coupled between the first and second load portions, and configured to provide a correction current to the output node through the first load portion.

Description

CROSS-REFERENCES TO RELATED APPLICATION[0001]The application is a continuation-in-part of the U.S. patent application Ser. No. 14 / 458,386 filed on Aug. 13, 2014 and titled “AMPLIFICATION CIRCUIT ADJUSTING DUTY CYCLE OF OUTPUT SIGNAL”, which is incorporated herein by reference in its entirety.BACKGROUND[0002]1. Technical Field[0003]Embodiments of the present invention generally relate to a semiconductor apparatus, and more particularly, to an amplification circuit capable of buffering or amplifying an input signal to output an output signal and a receiver including the same.[0004]2. Related Art[0005]In an electronic system in which one device (e.g., master device) controls the other devices (e.g., slave device), the master device sends a control signal and data to the slave device through a plurality of buses, and the slave device sends data to the master device through a plurality of buses.[0006]As described above, the master device and the slave device operate in response to signal...

AI Technical Summary

Benefits of technology

The patent describes a receiving device that includes multiple stages of amplification for a variety of purposes. The device includes a first buffer to amplify the input signal, a second buffer to amplify the output of the first buffer, and a third buffer to amplify the output of the second buffer. The first buffer includes a duty cycle adjustment to provide a correction current to the output nodes. The second buffer includes a second input and a second current mirror to provide an amplified current to the first input and load portions. The third buffer includes a second input and a second current mirror to provide an amplified current to the second input and load portions. The technical effect of this invention is to improve the accuracy and reliability of the received signal.

Problems solved by technology

However, various factors such as process variation and voltage variation may cause errors.

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