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Device and Method for Scheduling Commands in a Solid State Drive to Reduce Peak Power Consumption Levels

a solid-state drive and command scheduling technology, applied in the direction of instruments, input/output to record carriers, climate sustainability, etc., can solve the problems of increasing the peak current demand beyond, increasing current demands and current surges, and ssds may need larger or more capable power supplies

Active Publication Date: 2017-03-30
KIOXIA CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The patent describes a way to schedule commands in an SSD (solid state drive) that helps reduce sudden spikes and surges in power consumption. This is done by analyzing the current usage patterns of the command to be performed and other commands that are currently being processed. The result is a more efficient and effective way to handle commanded data transfers in the SSD.

Problems solved by technology

Further, when an SSD device uses more than one channel, multiple current spikes can occur simultaneously over multiple memory devices on multiple channels, which causes higher current demands and current surges.
However, the cumulative effect of simultaneous current surges across multiple channels of an SSD device may increase peak current demand beyond the energy levels that bulk capacitors can provide.
Therefore, larger or more capable power supplies may be required for the SSD.
In addition, increased peak-power consumption and the cumulative effect of multiple peak-power demands can result in signal integrity problems between the NAND flash memory devices and the SSD controller due to attendant shifts in supply voltages and “ground bounce” (displacement of the zero-voltage (V) reference).
Decoupling capacitors placed close to the NAND flash memory devices can be used to ameliorate this unwanted effect, but unfortunately do not eliminate it.
However, the solution taught by Kim only addresses the period of switching of the bus signals on the channel between the SSD controller and the flash memory devices, which is the period when a command is sent from the controller to the flash memory device.
Therefore, the solution taught by Kim is incomplete.
Another problem with the above solution taught by Kim is the length of the timing delay itself especially if the delay is based on a high frequency common clock.
However, Yurzola effectively limits, or chokes, the number of simultaneous commands of the same type in use without specially addressing the problem at hand, i.e., the coincidence or overlap of concurrent high current peaks or current spikes across multiple memory devices resulting in excessive peak-power demands being made by the SSD.

Method used

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  • Device and Method for Scheduling Commands in a Solid State Drive to Reduce Peak Power Consumption Levels

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Embodiment Construction

[0039]FIG. 1 illustrates a prior art structure of a basic SSD storage device 100 comprising a SSD controller 110, volatile memory buffer 115 and a non-volatile memory array 140, the SSD controller 110 communicating with a host computer system (not shown) via an interface 120. The non-volatile memory array 140 may include individual NAND flash memory devices 160a-d, 161a-d, 162a-d, 163a-d, communicating to the SSD controller 110 via memory channels 150-153. More particularly, SSD controller 110 is connected via a first bus (i.e., channel 0) to NAND flash memory devices 160a-160d. Similarly, SSD controller 110 is connected via a second bus (i.e., channel 1) to NAND flash memory devices 161a-161d, and is connected via a third bus (i.e., channel 2) to NAND flash memory devices 162a-162d, and is connected via a fourth bus (i.e., channel 3) to NAND flash memory devices 163a-163d. The SSD device 110 also connects via a separate bus to a separate memory 115, generally a volatile dynamic RAM...

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Abstract

The current consumed by flash memory devices on the channels of a solid-state drive (SSD) device will be in the form of a time varying waveform, characterized mainly by the types of commands being processed, and are often in the form of periods of constant levels interspersed with very short high current peaks or spikes. When multiple commands are being processed, significant high current peak demands and current surges can occur. The invention described herein is a device and method for scheduling commands to be processed in order to reduce the size of peak current demands and current surges. According to one embodiment of the invention, the device and method for scheduling a command uses look-up tables to determine the time to initiate the processing of the command by the flash memory devices.

Description

FIELD OF THE INVENTION[0001]The invention generally relates to a device and method for scheduling commands to flash memory devices in a solid-state drive (SSD) to reduce the size of peak current demands and current surges.BACKGROUND OF THE INVENTION[0002]A solid-state drive (SSD) is a storage device which typically includes a memory controller attached to non-volatile solid-state memory, typically NAND flash memory, and may communicate with a host to store data received from the host or to retrieve stored data requested by the host. Typically, an SSD controller is linked to an array of NAND flash memory devices arranged as a number of devices on a number of channels, where a number of operations may be conducted in parallel or simultaneously across the number of devices on a number of the channels (memory buses).[0003]During normal operation, the current consumption of an SSD is dependent on many factors, for example, the number and type of operations performed on the SSD.[0004]In n...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): G06F3/06
CPCG06F3/0625G06F3/0688G06F3/0659G06F3/0613G06F13/1689Y02D10/00G06F1/3275G06F3/0679G06F12/0246
Inventor MARGETTS, JULIENCALDER, GARY JAMES
Owner KIOXIA CORP