Chip Warpage Reduction Via Raised Free Bending & Re-entrant (Auxetic) Trace Geometries
a trace geometrie and free bending technology, applied in the direction of transportation and packaging, layered products, other domestic articles, etc., can solve problems such as interfacial stresses, and achieve the effect of relieving stress
Inactive Publication Date: 2019-08-15
THE BOARD OF TRUSTEES OF THE UNIV OF ARKANSAS
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Benefits of technology
The present invention is about using a method called "auxetic behavior" to create structures that have less warping and can hold electronic components more tightly. This method involves layering materials in a way that counteracts the expansion and contraction that occurs with changes in temperature. By using bending moments and a specific design, the invention can create structures that are more stable and reliable. This can lead to smaller and more efficient electronic components.
Problems solved by technology
A key challenge in microelectronic assembly arises when chip warpage, resulting from thermal expansion mismatch in layered materials, drives incompatibility in assembly and can result in interfacial stresses when experiencing temperature swings native to device operation.
Method used
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[0041]Detailed embodiments of the present invention are disclosed herein; however, it is to be understood that the disclosed embodiments are merely exemplary of the invention, which may be embodied in various forms. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention in virtually any appropriately detailed method, structure or system. Further, the terms and phrases used herein are not intended to be limiting, but rather to provide an understandable description of the invention.
[0042]Most electronic devices are made of multiple materials stacked in layered form, where usually copper and silicon dominate the material composition along with some dielectric insulating layers. Cu and Si have very different thermal expansions when heated, which leads to interfacial stresses where they are bonded together. These stresse...
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A microelectronic device and method of making the same including a substrate and at least one expansion layer that adds stress to the substrate when said substrate expands.
Description
RELATED APPLICATIONS[0001]This application claims priority to U.S. Provisional Application No. 62 / 631,337 filed on Feb. 15, 2018, which is hereby incorporated in its entiretySTATEMENT REGARDING FEDERALLY SPONSORED RESEARCH & DEVELOPMENT[0002]This invention was made with government support by the National Science Foundation No. 14495548. The government has certain rights in the invention.INCORPORATION BY REFERENCE OF MATERIAL SUBMITTED ON A COMPACT DISC[0003]Not applicable.BACKGROUND OF THE INVENTION[0004]A key challenge in microelectronic assembly arises when chip warpage, resulting from thermal expansion mismatch in layered materials, drives incompatibility in assembly and can result in interfacial stresses when experiencing temperature swings native to device operation. In design of electronic routing layers in Si chips and their associated packaging, linear copper structures are traditionally used to deliver current and signals to and from the active elements in the device. The l...
Claims
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Login to View More IPC IPC(8): H01L23/373B32B9/04H01L23/00H01L21/48
CPCH01L23/3735B32B9/041H01L23/562H01L21/4882B32B2307/30B32B2457/00H01L23/373H01L23/367H01L2924/10253H01L2224/13101H01L2224/81815H01L2924/10272H01L2924/1033H01L23/49838H01L24/13H01L24/81H01L23/5221H01L2924/014H01L2924/00014H01L24/24Y10T428/24942
Inventor HUITINK, DAVIDHARRIS, JOHN
Owner THE BOARD OF TRUSTEES OF THE UNIV OF ARKANSAS