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Fuse array structure

a fuse array and array technology, applied in the field of fuse array structure, can solve the problem of difficulty in maintaining sufficient isolation between electrical components in the fuse array structur

Pending Publication Date: 2022-03-17
NAN YA TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

The buried word line configuration enhances electrical isolation, ensuring reliable dielectric breakdown and improving the overall reliability of the fuse array structure by maintaining sufficient distance between the buried word line and the fuse gate structure.

Problems solved by technology

Accordingly, it is difficult to maintain sufficient isolation between electrical components in the fuse array structure.

Method used

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Examples

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Embodiment Construction

[0036]The following description of the disclosure accompanies drawings, which are incorporated in and constitute a part of this specification, and illustrate embodiments of the disclosure, but the disclosure is not limited to the embodiments. In addition, the following embodiments can be properly integrated to complete another embodiment.

[0037]References to “one embodiment,”“an embodiment,”“exemplary embodiment,”“other embodiments,”“another embodiment,” etc. indicate that the embodiment(s) of the disclosure so described may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Further, repeated use of the phrase “in the embodiment” does not necessarily refer to the same embodiment, although it may.

[0038]As used herein, the term “anti-fuse” refers to a semiconductor device which is a normally open circuit. The anti-fuse can be “blown” to become a short circuit when a programming ...

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Abstract

The present disclosure provides a semiconductor structure with a fuse array structure having a buried word line disposed within a substrate. The semiconductor structure includes a substrate having a first surface, a first doped region disposed under the first surface, a second doped region disposed under the first surface, and a recess indented into the substrate and disposed between the first doped region and the second doped region; a first gate structure disposed over the first doped region and electrically connected to a first bit line; a second gate structure to disposed over the first surface of the substrate and electrically connected to a second bit line; and a buried word line disposed within the first recess and disposed between the first gate structure and the second gate structure. The second gate structure is at least partially disposed within the second recess of the substrate.

Description

PRIORITY CLAIM AND CROSS-REFERENCE[0001]This application claims the priority benefit of U.S. provisional application Ser. No. 62 / 785,359 filed on Dec. 27, 2018. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.CROSS-REFERENCE TO RELATED APPLICATION[0002]This application is a divisional application of U.S. Non-Provisional Application No. 16 / 677,104 filed on Oct. 29, 2019. The entirety of the above-mentioned patent application is hereby incorporated by reference herein and made a part of this specification.TECHNICAL FIELD[0003]The present disclosure relates to a semiconductor structure, and particularly relates to a fuse array structure having a buried word line disposed within a substrate.DISCUSSION OF THE BACKGROUND[0004]Semiconductor devices are essential for many modern applications. Among the semiconductor devices, memory devices such as dynamic random access memory (DRAM) have assumed an impor...

Claims

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Application Information

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Patent Type & Authority Applications(United States)
IPC IPC(8): H01L27/108H10B12/00H10B69/00
CPCH01L27/10897H01L27/10823G11C11/34G11C7/18H10B12/30H10B20/25H01L23/5252H10B12/50H10B12/34
Inventor LIN, SHIAN-JYH
Owner NAN YA TECH