ASIC routing architecture

Abstract

An embodiment of the invention includes a routing architecture with a plurality of predesigned layers and a custom layer. The structure includes a plurality of parallel vertical tracks. In one layer, the tracks include a pin coupled to an input / output of an underlying function block and the track also includes a first portion of an unbroken conductive path. A second portion of the unbroken conductive path is formed under the pin in at least a second predesigned layer. In some embodiments, the second portion of the unbroken conductive path is formed in the second predesigned layer for some tracks and a third predesigned layer for other tracks. Hence, pins and unbroken conductive paths are multiplexed in a single track. In addition, the second predesigned layer further includes long horizontal conductors. When using the predesigned layers, the custom layer can be structured to provide free global routing with distinct local routing, all while using an array structure independent of routing channels and without rendering any function blocks unusable. Moreover, a structure in accordance with the invention includes conductors for clock distribution which can be used to form multiple independent clock domains. The structure is compact, yet flexible and can be customized in some embodiments with 1-2 masks.

Description

FIELD OF INVENTION[0001]The present invention generally relates to integrated circuits, and more specifically, to a routing architecture for interconnecting various IC devices and function blocks to form a customized circuit.BACKGROUND OF THE INVENTION[0002]ASICs (application specific integrated circuits) are widely used by electrical design engineers to include specialized circuitry in their designs using only a single chip. The term “ASIC” actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, module based arrays, and gate arrays. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate and / or customize.[0003]In forming ASICs generally, several layers will be required. FIG. 1 shows a cross-sectional view of a generic integrated circuit. First, active layers are formed on a semiconductor substrate. The active layers 110 incl...

AI Technical Summary

Benefits of technology

[0021]In some embodiments, one of the predesigned layers further includes conductors useful for clock distribution. In some embodiments, by using these clock conductors multiple independent clock domains can be easily formed.

[0022]As a result, a routing structure is formed over the function blocks in a manner that is independent of any channels and that does not render any function blocks unusable. Such a structure further provides free global routing while providing distinct local routing. Finally, because the structure allows routing both above and below pins and other parts of the routing fabric, the structure is not only compact and flexible, but permits one-mask customization.

Problems solved by technology

Nonetheless, before the custom layer is placed, the pins and freeways remain uncoupled to, and thus independent of, one another.

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