Semiconductor device and fabrication method of the same
a technology of semiconductor devices and fabrication methods, applied in semiconductor devices, semiconductor/solid-state device details, electrical apparatus, etc., can solve the problems of inability to respond to complex wiring and present mcp structures, and achieve the effect of reducing the size of packaging areas
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first embodiment
[0064]FIG. 1 is a cross-sectional view illustrating the structure of a semiconductor device in a first embodiment. FIGS. 2A to 8V are cross-sectional views illustrating a fabrication method of the semiconductor device in the first embodiment.
[0065]In a semiconductor device 100 shown in FIG. 1, a 2nd semiconductor chip 20 (second semiconductor chip) formed with integrated circuits (not shown) is mounted on a 1st semiconductor chip 10 (first semiconductor chip) formed with integrated circuits (not shown) as layered in the direction nearly orthogonal to the front side of the chip, and they are encapsulated with an encapsulating resin 40.
[0066]The 1st semiconductor chip 10 has pad electrodes 12 electrically connected to the integrated circuits thereon, and has a first insulating film 14 (polyimide, for example) formed in the portions other than the pad electrodes 12. The 1st semiconductor chip 10 is formed with a first rewiring layer 16 for electrically connecting the pad electrodes 12 ...
second embodiment
[0081]FIGS. 13A and 13B are partial schematic diagrams illustrating the metal post interconnect of a semiconductor device in a second embodiment; FIG. 13A is a partial plan view, and FIG. 13B is a partial cross-sectional view. FIGS. 14A and 14B are partial schematic diagrams illustrating the metal post interconnect of a traditional semiconductor device; FIG. 14A is a partial plan view, and FIG. 14B is a partial cross-sectional view.
[0082]In the second embodiment, as shown in FIGS. 13A and 13B, a first rewiring layer 16 (second wiring) is formed so as to cover adjacent pad electrodes 12 of a 1st semiconductor chip 10, and a first metal post interconnect 18 is formed on the first rewiring layer 16 so as to position the central axis near the center of the surface of the first rewiring layer 16. The configurations other than this are the same as those in the first embodiment, thus omitting the description.
[0083]Generally, as shown in FIGS. 14A and 14B, a metal post interconnect 64 is fo...
third embodiment
[0085]FIGS. 15A and 15B are schematic diagrams illustrating the structure of a semiconductor device in a third embodiment; FIG. 15A is a plan view, and FIG. 15B is a cross-sectional view.
[0086]In a semiconductor device 100 shown in FIGS. 15A and 15B, scribing line recognition posts 70 are formed at four corners on a 1st semiconductor chip 10 as exposed from an encapsulating resin 40, and the device is separated into pieces by a scribe blade 62, for example, along the scribing line recognition posts 70. For example, the scribing line recognition posts 70 can be formed as similar to the metal post interconnects 18 and 28. The other configurations are the same as those in the second embodiment, thus omitting the description.
[0087]Generally, when an inexpensive, opaque resin is used as the encapsulating resin 40, the scribing line (grid line) of the 1st semiconductor chip 10 cannot be observed and scribing (separating the device into pieces) is impossible. Therefore, an expensive, trans...
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