Method for multiple spacer width control

Abstract

A method of forming pluralities of gate sidewall spacers each plurality comprising different associated gate sidewall spacer widths including providing a first plurality of gate structures; blanket depositing a first dielectric layer over the first plurality of gate structures; blanket depositing a second dielectric layer over the first dielectric layer; etching back through a thickness of the first and second dielectric layers; blanket depositing a first photoresist layer to cover the first plurality and patterning to selectively expose at least a second plurality of gate structures; isotropically etching the at least a second plurality of gate structures for a predetermined time period to selectively etch away a predetermined portion of the first dielectric layer; and, selectively etching away the second dielectric layer to leave gate structures comprising a plurality of associated sidewall spacer widths.

Description

FIELD OF THE INVENTION[0001]This invention generally relates to microelectronic integrated circuit (IC) semiconductor device fabrication and more particularly to a method for multiple spacer width control in forming multiple transistor structures on a semiconductor wafer die.BACKGROUND OF THE INVENTION[0002]With increasing demands for embedded memory type structures, mixed-signal circuits, and system on chip (SOC) IC design, it has become necessary to form multiple transistor structures on a single die to achieve integrated functioning of the different transistor structures. For example, transistors with different structures and functions typically operate under different current and voltage parameters requiring different LDD widths and depths for the various transistors. The width of the LDD region is typically controlled by the width of spacers formed adjacent to a semiconductor gate structure to act as a mask before or following one or more doping processes, for example ion impla...

AI Technical Summary

Problems solved by technology

Although methods have been proposed in the prior art for forming multiple width sidewall spacers, the methods generally require an excessive number of photoresist patterning processes and etching processes and / or deposition processes to form gate sidewall spacers of different widths for different transistor designs formed on a single wafer or die.

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