Delay locked loop

Abstract

A delayed locked loop, capable of a duty cycle compensation, resets if a phase difference between outputs from delay blocks in the delay locked loop is over a predetermined amount after a delay locking state is achieved. The delay locked loop includes a duty cycle compensator for receiving first and second clocks and a reset control block for resetting the delay locked loop if a phase difference between the first and second clocks is over a predetermined amount after the delay locked loop achieves a delay locking state.

Description

FIELD OF INVENTION[0001]The present invention relates to a delay locked loop for use in a computer system or a semiconductor device such as a memory device; and, more particularly, to a delay locked loop (DLL) having an ability for duty cycle compensation.[0002]This application claims priority to Korean Patent Application No. 2005-0091681 filed Sep. 29, 2005 and Korean Patent Application No. 2006-0049120 filed May 31, 2006.BACKGROUND[0003]In a high speed synchronous semiconductor memory device such as a double data rate synchronous dynamic random access memory (DDR SDRAM), data is transferred (input from or output to) to other devices in synchronization with an external clock signal. That is, the high speed synchronous semiconductor memory device such as the DDR SDRAM performs an input or output operation in synchronization with not only a rising edge but also a falling edge of the external system clock signal. Typically, in a system or a circuit including a semiconductor memory, a ...

AI Technical Summary

Benefits of technology

The present invention provides a delay locked loop (DLL) that can compensate for duty cycle and reset if there is a phase difference between outputs from delay blocks in the loop. This allows for better synchronization of timing for outputting data responsive to a read command with an external clock. The invention also includes a reset control block that compares the phase of delayed clocks to reset the delay locked loop. This ensures that the output data is synchronized with the external clock.

Problems solved by technology

If either the input external clock or the internal clock is distorted, the delay locked loop can generate faulty DLL clocks and, accordingly, the semiconductor memory device can operate abnormally due to the faulty DLL clocks.

However, in the semiconductor memory device, the internal clock may not have a symmetrical waveform because an input clock is not symmetrical or the duty ratio is distorted by internal operations.

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