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Cavity-type integrated circuit package

a technology of integrated circuits and cavities, applied in the direction of electrical equipment, semiconductor devices, semiconductor/solid-state device details, etc., can solve the problems of inability to support the inner leads of these packages, the cost of packages is prohibitive, and the electrical impedance of wire bonds is reduced, and the signal distortion is reduced. , the effect of reducing the electrical impedance of the wire bond

Active Publication Date: 2010-06-08
UTAC HEADQUARTERS PTE LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Benefits of technology

[0010]In one aspect of the invention, an air cavity in the interior of the package body and the clamped portion of the contacts inhibits mold flash from contaminating a surface thereof, providing a clean wire bondable surface.
[0011]Advantageously, the cavity integrated circuit package according to an aspect of the present invention includes wire bonds that span air which has a low dielectric constant compared to molding compound, providing lower electrical impedance of the wire bonds and reduced signal distortion at high frequencies.

Problems solved by technology

However, these packages are cost prohibitive.
Again, these packages are cost prohibitive as they employ a substrate rather than a less-expensive leadframe.
However, the inner leads of these packages are not supported and the mold flash must be cleaned from the leads for the gold wire to stick to the inner leads during wire bonding.
Cleaning and wire bonding is difficult and therefore is not always successful.

Method used

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  • Cavity-type integrated circuit package
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Examples

Experimental program
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Effect test

Embodiment Construction

[0015]Referring to the figures, a process for fabricating a cavity-type integrated circuit package is described. The integrated circuit package is indicated generally by the numeral 20. The process includes supporting a leadframe strip 22 in a mold. The leadframe strip 22 includes a die attach pad 24 and a row of contact pads 26 circumscribing the die attach pad 24. A package body 28 is molded in the mold such that opposing surfaces of the die attach pad 24 and of the contact pads 26 are exposed. A semiconductor die 30 is mounted to the die attach pad 24. Various ones of the contact pads 26 are wire bonded to the semiconductor die 30 and a lid 32 is mounted on the package body 28 to thereby enclose the semiconductor die 30 and the wire bonds 34 in a cavity of the integrated circuit package 20.

[0016]For ease of understanding, the figures provided and described herein show the basic steps in fabricating the cavity-type integrated circuit package 20 according to the present invention.

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PUM

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Abstract

A process for fabricating a cavity-type integrated circuit includes supporting a leadframe strip in a mold. The leadframe strip includes a die attach pad and a row of contact pads circumscribing the die attach pad. A package body is molded in the mold such that opposing surfaces of the die attach pad and of the contact pads are exposed. A semiconductor die is mounted to the die attach pad. Various ones of the contact pads are wire bonded to the semiconductor die and a lid is mounted on the package body to thereby enclose the semiconductor die and the wire bonds in a cavity of the integrated circuit package.

Description

CROSS REFERENCE TO RELATED APPLICATIONS[0001]This application is a continuation-in-part of U.S. patent application Ser. No. 10 / 232,678, filed Sep. 3, 2002, now U.S. Pat. No. 6,821,817, issued Nov. 23, 2004.FIELD OF THE INVENTION[0002]The present invention relates in general to integrated circuit packaging, and more particularly to a cavity-type integrated circuit package.BACKGROUND OF THE INVENTION[0003]Cavity-type IC packages are useful in imaging devices such as CMOS imaging or CCD display applications for still or video cameras. The package includes a die at the base of a cavity and a clear lid epoxied on top. The use of a cavity-type IC package is advantageous for high frequency applications as the gold interconnect wires between the die attach pad and the contacts span an air gap rather than travelling through mold compound. The air has a lower dielectric constant than the mold compound and therefore the electrical impedance of the gold wire is much lower when the wire runs thr...

Claims

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Application Information

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IPC IPC(8): H01L23/495
CPCH01L23/10H01L23/49861H01L24/48H01L24/83H01L23/24H01L2924/0665H01L2924/01033H01L24/49H01L2924/3011H01L2924/166H01L2924/16195H01L2924/16152H01L2924/14H01L2924/07802H01L2924/01079H01L2924/01047H01L2924/01046H01L2924/01029H01L2924/01028H01L2924/01014H01L2924/01013H01L2924/01006H01L2924/01005H01L2224/8592H01L24/28H01L24/45H01L2224/2919H01L2224/32245H01L2224/45144H01L2224/48091H01L2224/48227H01L2224/48247H01L2224/484H01L2224/48599H01L2224/49109H01L2224/73265H01L2224/83101H01L2224/8385H01L2924/00014H01L2924/00H01L2924/00012H01L2924/181H01L24/73H01L2224/85399H01L2224/05599
Inventor MCLELLAN, NEILWAGENHOFFER, KATHERINELIN, GERALDINE TSUI YEEKIRLOSKAR, MOHAN
Owner UTAC HEADQUARTERS PTE LTD